A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.

A MEMS device package comprising a first die of semiconductor material including a contact pad and a second die of semiconductor material stacked on the first die. The second die is smaller than the first die. The second die includes a contact pad, and a conductive wire is coupled between the contact pad of the first die and a contact pad of the second die. A mold compound is on the second die and the first die. A vertical connection structure is on the contact pad of the second die. The vertical connection structure extends through the mold compound.

A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.

An electronic package structure includes a first printed circuit board, a second printed circuit board and first space columns. The first printed circuit board has a first surface and a through hole. The second printed circuit board has a second surface facing the first surface. Each first space column is interconnected between the first surface and the second surface. An encapsulation layer is filled between the first and second printed circuit boards and among the first space columns so as to define a hollow chamber. A MEMS microphone component located within the hollow chamber is located on the first surface and aligned with the through hole. A sensing component is located within the hollow chamber.

A microphone package structure includes a substrate, a metal housing, a MEMS microphone component and at least one integrated circuit component. The substrate has a first surface and a second surface that are opposite to each other. The metal housing is located on the first surface such that the substrate and the metal housing collectively define a hollow chamber. The MEMS microphone component is located on the metal housing and within the hollow chamber. The at least one integrated circuit component is located within a region of the second surface on which the metal housing has a vertical projection.

A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package.

An apparatus is described that includes a semiconductor chip package. The semiconductor chip package includes a plurality of stacked semiconductor chips. The plurality of stacked semiconductor chips are stacked with a lateral offset, wherein, the lateral offset exposes first wirebond pads of the plurality of stacked semiconductor chips. The semiconductor chip package further includes a substrate interposer having second wirebond pads. The semiconductor chip package further includes wirebonds connecting the first wirebond pads and the second wirebond pads. The semiconductor chip package further includes a package substrate. The semiconductor chip package further includes vias that are electrically connected to the substrate interposer and a first surface of the package substrate. The semiconductor chip package further includes package level I/Os on a second surface of the package substrate that is opposite the first surface of the package substrate.

A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.

A package device includes a circuit layer, at least one conductive segment, an encapsulant and a redistribution layer. The conductive segment is disposed on the circuit layer and has a first surface and a second surface. The encapsulant encapsulates at least a portion of the conductive segment and has a first upper surface. A first portion of the first surface and at least a portion of the second surface of the conductive segment are disposed above the first upper surface of the encapsulant. The redistribution layer is disposed on the encapsulant, the first portion of the first surface of the conductive segment, and the second surface of the conductive segment.

A MEMS device package comprising a first die of semiconductor material including a contact pad and a second die of semiconductor material stacked on the first die. The second die is smaller than the first die. The second die includes a contact pad, and a conductive wire is coupled between the contact pad of the first die and a contact pad of the second die. A mold compound is on the second die and the first die. A vertical connection structure is on the contact pad of the second die. The vertical connection structure extends through the mold compound.