A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.

A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.

A packaged antenna circuit structure suitable for 5G use includes a shielding layer, an electronic component, conductive pillars, a first insulation layer, a first stacked structure, an antenna structure, and a second stacked structure. The shielding layer defines a groove to receive the electronic component. The conductive pillars on the shielding layer surround the groove. The first insulation layer covers the shielding layer, the electronic component, and the conductive pillars. The first stacked structure is stacked on a side of the first insulation layer and includes a ground line connecting to the conductive pillars. The antenna structure is stacked on a side of the first stacked structure away from the first insulation layer and connected to the electronic component by the first stacked structure. The second stacked structure is stacked on a side of the first insulation layer away from the first stacked structure.

A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.

In an embodiment, a method includes forming a conductive feature adjacent to a substrate; treating the conductive feature with a protective material, the protective material comprising an inorganic core with an organic coating around the inorganic core, the treating the conductive feature comprising forming a protective layer over the conductive feature; and forming an encapsulant around the conductive feature and the protective layer. In another embodiment, the method further includes, before forming the encapsulant, rinsing the protective layer with water. In another embodiment, the protective layer is selectively formed over the conductive feature.

A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

An embedded module according to the present invention includes a base substrate having a multi-layer wiring, at least two semiconductor chip elements having different element thicknesses, each of the semiconductor chip element having a first surface fixed to the base substrate and having a connection part on a second surface, an insulating photosensitive resin layer enclosing the semiconductor chip elements on the base substrate and being formed by a first wiring photo via, a second wiring photo via, and a wiring, the first wiring photo via electrically connected to the connection part of the semiconductor chip elements, the second wiring photo via arranged at the outer periphery of each of the semiconductor chip elements and electrically connected to a connection part of the base substrate, the wiring arranged so as to be orthogonal to and electrically connected to the first wiring photo via and the second wiring photo via.

A semiconductor package may include a redistribution substrate including first and second surfaces opposite each other, a first semiconductor chip on the first surface, a first molding portion on a side surface of the first semiconductor chip, a second semiconductor chip between the first semiconductor chip and the redistribution substrate, a second molding portion between the redistribution substrate and the first molding portion and on a side surface of the second semiconductor chip, bump patterns between the second semiconductor chip and the redistribution substrate, and a mold via penetrating the second molding portion and electrically connecting the first semiconductor chip to the redistribution substrate. The redistribution substrate may include first and second redistribution patterns sequentially in an insulating layer. The mold via may contact the second redistribution pattern, and the bump patterns may contact the first redistribution pattern.

An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.