A method of forming a redistribution structure includes providing a dielectric layer. The dielectric layer is patterned to form a plurality of via openings. A seed layer is formed on the dielectric layer and filling in the plurality of via openings. A patterned conductive layer is formed a on the seed layer, wherein a portion of the seed layer is exposed by the patterned conductive layer. The portion of the seed layer is removed by using an etching solution, thereby forming a plurality of conductive lines and a plurality of vias. During the removing the portion of the seed layer, an etch rate of the patterned conductive layer is less than an etch rate of the seed layer.

A semiconductor device has first and second dies forming a die stack. Molding material encapsulates the die stack and forms an upper molded surface of the die stack. First conductive traces are coupled to the first die and extend from between the first and second die to corresponding first via locations in the molding material beyond a first side edge of the die stack. Second conductive traces coupled to an active surface of the second die opposite the first die extend to corresponding second via locations. Each first via location is vertically aligned with one of the second via locations. Through mold vias extend through the molding material between vertically aligned via locations to contact with corresponding conductive traces of the first and second dies, while the molding material that extends between the first conductive traces and the upper molded surface is free from any TMV.

A redistribution structure for a semiconductor device and a method of forming the same are provided. The semiconductor device includes a die encapsulated by an encapsulant, the die including a pad, and a connector electrically connected to the pad. The semiconductor device further includes a first via in physical contact with the connector. The first via is laterally offset from the connector by a first non-zero distance in a first direction. The first via has a tapered sidewall.

A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.

Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

An optoelectronic device package includes a first redistribution layer (RDL), a first electronic die disposed over the first RDL, wherein an active surface of the first electronic die faces the first RDL. The optoelectronic device package further includes a second electronic die disposed over the first RDL, and a photonic die disposed over and electrically connected to the second electronic die. An active surface of the second electronic die is opposite to the first RDL.

An electronic device package includes an encapsulated electronic component, a substrate, a conductor and a buffer layer. The encapsulated electronic component includes a redistribution layer (RDL) and an encapsulation layer. The first surface is closer to the RDL than the second surface is. The encapsulation layer includes a first surface, and a second surface opposite to the first surface. The substrate is disposed on the second surface of the encapsulation layer. The conductor is disposed between the substrate and the encapsulated electronic component, and electrically connecting the substrate to the encapsulated electronic component. The buffer layer is disposed between the substrate and the encapsulated electronic component and around the conductor.

An apparatus for securing a wafer includes a chuck, at least one O-ring disposed on the chuck, a vacuum system connected to the chuck, such that the vacuum system comprises a plurality of vacuum holes through the chuck connected to one or more vacuum pumps, and a controller configured to control the height of the at least one O-ring relative to the top surface of the chuck. The controller is connected to pressure sensors capable of detecting a vacuum. The at least one O-ring may include a plurality of O-rings.

A substrate having an electronic component embedded therein includes a core structure including a first insulating body and core wiring layers and having a cavity penetrating through a portion of the first insulating body, an electronic component disposed in the cavity, an insulating material covering at least a portion of each of the core structure and the electronic component and disposed in at least a portion of the cavity, a wiring layer disposed on the insulating material, and a build-up structure disposed on the insulating material and including a second insulating body and a build-up wiring layer. A material of the first insulating body has a coefficient of thermal expansion (CTE) less than a CTE of the second insulating body, and the insulating material has a CTE less than a CTE of a material of the second insulating body.