A radio-frequency module including a mounting substrate that has mounting faces opposed to each other; a PA that is mounted on the mounting face, that is a radio-frequency component, and that has an emitter terminal; a through electrode that is connected to the emitter terminal of the PA and that passes through the mounting faces of the mounting substrate; and a ground terminal connected to the through electrode.

A device including a stack of dies. Each of the dies can have unit stair-step conductive paths of connection features which include through-die via structures and routing structures. The unit stair-step conductive paths of one of the dies can be interconnected to another one of the unit stair-step conductive paths of another one of the dies to form one of a plurality conductive stair-case structures through two or more of the dies. The unit stair-step conductive paths can be connected to reduce signal cross talk between the conductive stair-case structures whereby at least some of the conductive stair-case structures are connected to transmit a same polarity of electrical signals are spatially separated in a dimension that is perpendicular to a major surface of the dies. A method of manufacturing the device is also disclosed.

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.

Provided is a device housing made of materials containing at least an electrically conductive material, an image reading device, and an electrostatic capacitance detection device that can achieve electrical connection with a relatively small space while preventing deformation of the device housing. The device housing includes a housing made of materials containing at least an electrically conductive material and including an electrically conductive surface in at least part of the surface of the housing, a ground conductor being present on a plane different from the plane including the electrically conductive surface, and a ground auxiliary conductor disposed over a level difference existing between the plane including the electrically conductive surface and the plane including the ground conductor. The ground auxiliary conductor is an electrically conductive sheet to connect the electrically conductive surface to the ground conductor electrically.

A semiconductor package is configured to include a package substrate, a semiconductor chip disposed on the package substrate, and bonding wires. The package substrate includes a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer. The semiconductor chip includes a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column. The first column of chip pads are connected to the first column of bond fingers, respectively, through first bonding wires, and the second column of chip pads are connected to the second column of bond fingers, respectively, through second bonding wires.

A memory device includes a first semiconductor structure and a second semiconductor structure. The memory device further includes a bonding structure between the first semiconductor structure and the second semiconductor structure, the bonding structure comprising a first bonding pattern and a second bonding pattern in contact with each other, the first semiconductor structure being electrically connected with the second semiconductor structure through the bonding structure. The memory device further includes a shielding structure between the first semiconductor structure and the second semiconductor structure and surrounding the bonding structure, the shielding structure comprising a third bonding pattern and a fourth bonding pattern in contact with each other, the shielding structure being electrically connected with a biased voltage.

A package that includes a substrate, an integrated device, a first encapsulation layer and a void. The substrate includes a first surface. The integrated device is coupled to the first surface of the substrate. The first encapsulation layer is located over the first surface of the substrate and the integrated device. The first encapsulation layer includes an undercut relative to a side surface of the integrated device. The void is located between the integrated device and the first surface of the substrate. The void is laterally surrounded by the undercut of the encapsulation layer.

Semiconductor devices having multiple substrates and die stacks, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device includes a package substrate, and a first die stack mounted on the package substrate and including a plurality of first memory dies. The device can include a substrate mounted on the first die stack, the substrate including a plurality of routing elements. The device can also include a second die stack mounted on the substrate, the second die stack including a plurality of second memory dies. The device can further include a controller die mounted on the substrate. The controller die can be configured to communicate with the second die stack via the routing elements of the substrate. The device can include a mold material encapsulating the first die stack, the second die stack, the substrate, and the controller die.

Improve EM coupling for the wafer-bonding process from a first wafer to a second wafer by a shielding technique. Examples may include building an EM shield implemented by BEOL-stacks/routings, bonding contacts, and TSVs for a closed-loop shielding platform for the integrated device to minimize EM interference from active devices due to eddy currents. The shield may be implemented in the active device layer during a wafer-to-wafer bonding-process that uses two different device layers/wafers, an active device layer/wafer and a passive device layer/wayer. The shield may be designed by the patterned routings for both I/O ports and the GND contacts.

This patent application relates to microelectronic device packages with internal EMI shielding, methods of fabricating and related electronic systems. One or more microelectronic devices of a package including multiple microelectronic devices are EMI shielded, and one or more other microelectronic devices of the package are located outside the EMI shielding.