Stack assembly for radio-frequency applications. In some embodiments, a radio-frequency (RF) module can include a packaging substrate configured to receive a plurality of components, and an electro-acoustic device mounted on the packaging substrate. The RF module can further include a die having an integrated circuit and mounted over the electro-acoustic device to form a stack assembly. The electro-acoustic device can be, for example, a filter device such as a surface acoustic wave filter. The die can be, for example an amplifier die such as a low-noise amplifier implemented on a silicon die.

A package that includes a substrate, an integrated device, a first encapsulation layer and a void. The substrate includes a first surface. The integrated device is coupled to the first surface of the substrate. The first encapsulation layer is located over the first surface of the substrate and the integrated device. The first encapsulation layer includes an undercut relative to a side surface of the integrated device. The void is located between the integrated device and the first surface of the substrate. The void is laterally surrounded by the undercut of the encapsulation layer.

A method of forming a package comprises assembling at least one chip layer over a carrier substrate, the at least one chip layer including chip couplers and chips, each of the chips having a front side facing the carrier substrate and chip contacts formed on the front side, the couplers including first chip couplers, each of the first chip couplers having an upper side facing away from the carrier substrate and first bumps formed on the upper side. The method further comprises encapsulating the at least one chip layer to form a molded package structure, thinning the molded package structure to expose the first bumps, forming a metal layer on a side of the molded package structure where the first bumps are exposed, removing the carrier to expose another side of the molded package structure, and forming a redistribution layer and second bumps on the molded package structure.

A foldable doll includes: a doll body which is a hollow structure; a projection lamp disposed in the doll body; a power connector electrically connected to the projection lamp; a supporting assembly for supporting the doll body; a plurality of supporting rings sewn on the doll body; a blower connected to the doll body and electrically connected to the power connector. The projection lamp includes a lamp cover, a motor, and a projection unit. The motor includes a rotation shaft, and the projection unit is fixedly disposed on the rotation shaft and configured to emit and project light on the lamp cover. The blower is electrically connected to the power connector. In an unfolded state, the doll body is propped up by the supporting assembly, and in a folded state, the supporting assembly is detached from the doll body, and the doll body automatically collapses by gravity.

One embodiment is a microelectronic assembly including an assembly support structure; a first die including a pair of hot via comprising through-substrate-via (TSVs) extending through the first die between first and second sides thereof and a plurality of ground vias surrounding the pair of hot vias and extending through the first die between the first and second sides thereof. The first die further includes a pair of signal interconnect structures electrically connected to the pair of hot vias disposed on the second side of the first die. The assembly further includes a second die between the assembly support structure and the first die the pair of signal interconnect structures disposed on the first side thereof. The first die is connected to the second die via a signal die-to-die (DTD) interconnect structure including the signal interconnect structures of the first and second dies.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more stacks of microelectronic devices are located on the substrate, and microelectronic devices of the stacks are connected to vertical conductive paths external to the stacks and extending to the substrate and to lateral conductive paths extending between the stacks. Methods of fabrication are also disclosed.

An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.

A semiconductor package comprising a package substrate that has a recessed portion on a top surface thereof, a lower semiconductor chip in the recessed portion of the package substrate, an upper semiconductor chip on the lower semiconductor chip and the package substrate and having a width greater than that of the lower semiconductor chip, a plurality of first bumps directly between the package substrate and the upper semiconductor chip, and a plurality of second bumps directly between the lower semiconductor chip and the upper semiconductor chip. A pitch of the second bumps is less than that of the first bumps.

In one example, an electronic assembly comprises a first semiconductor device and a second semiconductor device. Each of the first semiconductor device and the second semiconductor devices comprises a substrate comprising a top surface and a conductive structure, an electronic component over the top surface of the substrate, a dielectric material over the top surface of the substrate and contacting a side of the electronic component, a substrate tab at an end of substrate and not covered by the dielectric material, wherein the conductive structure of the substrate is exposed at the substrate tab, and an interconnect electrically coupled to the conductive structure at the substrate tab of the first semiconductor device and the conductive structure at the substrate tab of the second semiconductor device. Other examples and related methods are also disclosed herein.

A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.