H01L2225/06558

Semiconductor device and manufacturing method thereof
11502057 · 2022-11-15 · ·

A semiconductor device includes a substrate having a plurality of pads on a surface of the substrate, a semiconductor chip that includes a plurality of metal bumps connected to corresponding pads on the substrate, a first resin layer between the surface of the substrate and the semiconductor chip, a second resin layer between the substrate and the semiconductor chip and between the first resin layer and at least one of the metal bumps, and a third resin layer on the substrate and above the semiconductor chip.

SEMICONDUCTOR PACKAGE INCLUDING A REDISTRIBUTION SUBSTRATE AND A METHOD OF FABRICATING THE SAME
20220359358 · 2022-11-10 ·

A semiconductor package includes: a package substrate; a first re-distribution layer disposed on the package substrate; a second re-distribution layer disposed between the package substrate and the first re-distribution layer; a connection substrate interposed between the first re-distribution layer and the second re-distribution layer, wherein a connection hole penetrates the connection substrate; a first semiconductor chip mounted on a first surface of the first re-distribution layer; a first connection chip mounted on a second surface, opposite to the first surface, of the first re-distribution layer and disposed in the connection hole; a second connection chip mounted on a first surface of the second re-distribution layer and disposed in the connection hole; and a first lower semiconductor chip mounted on a second surface, opposite to the first surface, of the second re-distribution layer.

Multi-page display screen and mobile phone including the same

The disclosure provides a multi-page display screen and a mobile phone including the same. The multi-page display screen includes a first display sub-screen and a second display sub-screen formed by flexible screens. The first display sub-screen and the second display sub-screen each includes a first half screen and a second half screen. The first half screen and the second half screen are pivotable and foldable relative to each other, and the first half screen and the second half screen can be unfolded relative to each other to constitute the first display sub-screen and the second display sub-screen respectively. Backs of the first half screens of the first display sub-screen and in the second display sub-screen are bonded together, such that the first display sub-screen and the second display sub-screen are arranged as book pages. The multi-page display screen makes it easy to switch to a page of a different mode.

RELIABILITY COMPENSATION FOR UNEVEN NAND BLOCK DEGRADATION

Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.

FABRICATION METHOD OF STACKED DEVICE AND STACKED DEVICE
20230098533 · 2023-03-30 ·

Provided is a stacked device comprising: a plurality of circuit layers each having a circuit portion; an insulating layer configured to cover a plurality of circuit portions included in a part of circuit layers of the plurality of circuit layers, and a plurality of conductive vias provided in the insulating layer and electrically connected to the plurality of circuit portions, wherein the conductive via electrically connected to a partial circuit portion of the plurality of circuit portions is electrically insulated on an end surface on an opposite side to the plurality of circuit portions and the partial circuit portion is broken at least partially along a stacking direction.

SEMICONDUCTOR PACKAGE
20230087607 · 2023-03-23 ·

A semiconductor package includes a substrate extending in a first direction and a second direction perpendicular to the first direction, a first semiconductor chip disposed on the substrate, the first semiconductor chip having a stepped portion, a second semiconductor chip disposed on the substrate and horizontally spaced apart from the first semiconductor chip in the first direction, a third semiconductor chip disposed on the second semiconductor chip and a bottom surface of the stepped portion, and an upper adhesive layer disposed between the second semiconductor chip and the third semiconductor chip, the upper adhesive layer contacting a portion of the bottom surface of the stepped portion.

Semiconductor package having molding member and heat dissipation member

A semiconductor package includes a package substrate, a first semiconductor chip disposed on the package substrate, at least one second semiconductor chip disposed on a region of an upper surface of the first semiconductor chip, a heat dissipation member disposed in another region of the upper surface of the first semiconductor chip and at least a region of an upper surface of the second semiconductor chip, and having an upper surface in which at least one trench is formed, and a molding member covering the first semiconductor chip, the second semiconductor chip, an upper surface of the package substrate, and side surfaces of the heat dissipation member, and filling the at least one trench while exposing the upper surface of the heat dissipation member.

Semiconductor device and semiconductor device manufacturing method
11482502 · 2022-10-25 · ·

A semiconductor device includes a substrate that includes a first insulating layer, a conductive layer on the first insulating layer, a second insulating layer on the conductive layer, and an opening that passes through the conductive layer and the second insulating layer and in which part of the conductive layer is exposed, a conductive material that contacts at least the first insulating layer and the part of the conductive layer in the opening, and a semiconductor chip that has an electrode extending towards the first insulating layer within the opening and contacting the conductive material.

Grounding techniques for backside-biased semiconductor dice and related devices, systems and methods

Semiconductor devices may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Methods of making semiconductor devices may involve supporting a backside-biased semiconductor die supported above a substrate, a backside surface of the backside-biased semiconductor die being spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Systems may include a sensor device, a nontransitory memory device, and at least one semiconductor device operatively connected thereto. The at least one semiconductor device may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be electrically connected to ground by wire bonds extending to the substrate.

Semiconductor package with EMI shield and fabricating method thereof

A semiconductor device with EMI shield and a fabricating method thereof are provided. In one embodiment, the semiconductor device includes EMI shield on all six surfaces of the semiconductor device without the use of a discrete EMI lid.