A package comprising a carrier, at least one electronic chip mounted on one side of the carrier, an encapsulant at least partially encapsulating the at least one electronic chip and partially encapsulating the carrier, and at least one component attached to an opposing other side of the carrier via at least one contact opening.

A device includes a driver circuit, a first semiconductor chip monolithically integrated with the driver circuit in a first semiconductor material, and a second semiconductor chip integrated in a second semiconductor material. The second semiconductor material is a compound semiconductor.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Processes for configuring a plurality of independent die packages for socketing. The packages are attached to a carrier wafer with a release film. The attached plurality of independent die packages are overmolded to provide a molded multi-die package. The molded multi-die package is planarized to expose the dies, singulated, and released from the carrier wafer. The singulated, molded multi-die packaging may be picked for further processing and placed into a socket. A plurality of molded, multi-die packages may be placed in a socket and operate as a computer system. The independent die packages may each perform and same computer application function or different computer application functions, and may have the same or different dimensions. The socket may have any of a number of configurations as may be needed.

A three-dimensional package structure includes an energy storage element, a semiconductor package body and a shielding layer. The semiconductor package body has a plurality of second conductive elements and at least one control device inside. The energy storage element is disposed on the semiconductor package body. The energy storage element including a magnetic body is electrically connected to the second conductive elements. The semiconductor package body or the energy storage element has a plurality of first conductive elements to be electrically connected to an outside device. The three-dimensional package structure is applicable to a POL, (Point of Load) converter.

An electronic module can include a first integrated device package comprising a first substrate and an electronic component mounted to the first substrate. A first vertical interconnect can be mounted to and electrically connected to the first substrate. The first vertical interconnect can extend outwardly from the first substrate. The electronic module can include a second integrated device package comprising a second substrate and a second vertical interconnect having a first end mounted to and electrically connected to the second substrate. The second vertical interconnect can have a second end electrically connected to the first vertical interconnect. The first and second vertical interconnects can be disposed between the first and second substrates.

A semiconductor device includes a printed wiring board; a first semiconductor module including a first package body and a first heat radiation surface on one surface of the first package body, another surface of the first package body, opposite to the first heat radiation surface, faces one face of the printed wiring board; a first heat radiator on the first heat radiation surface; a second semiconductor module including a second package body and a second heat radiation surface on one surface of the second package body, another surface of the second package body, opposite to the second heat radiation surface, faces another face of the printed wiring board; and a second heat radiator provided on the second heat radiation surface. The first and second semiconductor modules are arranged to overlap each other in a plan view. The second semiconductor module is connected in parallel to the first semiconductor module.

The present invention discloses a three-dimensional package structure. The first conductive element comprises a top surface, a bottom surface and a lateral surface. The conductive pattern disposed on the top surface of the first conductive element. A second conductive element is disposed on the conductive pattern. The first conductive element is electrically connected to the conductive pattern, and the second conductive element is electrically connected to the conductive pattern. In one embodiment, the shielding layer is a portion of the patterned conductive layer.

A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. Wire bonds are electrically coupled with one or more first package contacts at the first major surface of the encapsulation region, each wire bond having a portion contacted and surrounded by the encapsulation region. Second package contacts at an interconnect surface being one or more of the second major surface and the peripheral surfaces include portions of the wire bonds at such surface, and/or electrically conductive structure electrically coupled with the wire bonds.

A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.