A semiconductor device may include a first conductive plate, a plurality of semiconductor chips disposed on the first conductive plate, and a first external connection terminal connected to the first conductive plate. The plurality of semiconductor chips may include first, second, and third semiconductor chips. The second semiconductor chip may be located between the first semiconductor chip and the third semiconductor chip. A portion of the first conductive plate where the first external connection terminal is connected may be closest to the second semiconductor chip among the first, second, and third semiconductor chips. The first conductive plate may be provided with an aperture located between the portion of the first conductive plate where the first external connection terminal is connected and a portion of the first conductive plate where the second semiconductor chip is connected.

A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region.

An electronic device includes a lead frame, a first clip, a second clip, and a plurality of semiconductor devices. The first clip is stacked with the lead frame. The second clip stacked with the first clip and the lead frame. The second clip includes a first protrusion that engages the first clip and secures the second clip to the first clip. The semiconductor devices are conductively coupled to the lead frame via the first clip and the second clip.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

An electronic module includes a semiconductor package including a die carrier, a semiconductor transistor die disposed on the die carrier, an electrical conductor connected to the semiconductor die, and an encapsulant covering the die carrier, the semiconductor die, and the electrical conductor so that a portion of the electrical conductor extends to the outside of the encapsulant. The electronic module further includes an interposer layer on which the semiconductor package is disposed, and a heat sink through which a cooling medium can flow. The interposer layer is disposed on the heatsink.

A semiconductor device includes a printed wiring board; a first semiconductor module including a first package body and a first heat radiation surface on one surface of the first package body, another surface of the first package body, facing the first heat radiation surface, faces one face of the printed wiring board; a first heat radiator on the first heat radiation surface; a second semiconductor module including a second package body and a second heat radiation surface on one surface of the second package body, another surface of the second package body, facing the second heat radiation surface, faces another face of the printed wiring board; and a second heat radiator provided on the second heat radiation surface. The first and second semiconductor modules are arranged to overlap each other in a plan view. The second semiconductor module is connected in parallel to the first semiconductor module.

A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.

A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.

A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.

A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.