Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate that includes a chip region and an edge region around the chip region, and a semiconductor chip on the chip region of the redistribution substrate. The redistribution substrate includes a plurality of dielectric layers that are vertically stacked, a plurality of redistribution patterns on the chip region and in each of the dielectric layers, and a redistribution test pattern on the edge region and at a level the same as a level of at least one of the redistribution patterns.

A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

A package substrate includes; a conductive line extending in a first horizontal direction, a conductive pad on an upper surface of the package substrate and horizontally spaced apart from the conductive line in a second horizontal direction, and a protective layer covering the conductive line and including an opening selectively exposing a portion of the conductive pad. The opening has an elongated elliptical shape having a minor axis defined by a width extending in the first horizontal direction and a major axis defined by a length extending in the second horizontal direction.

A method includes attaching a first anisotropic conductive film including first conductive particles to a front surface of a substrate structure; compressing a first redistribution structure on the front surface of the substrate structure such that a first redistribution conductor of the first redistribution structure that is exposed is electrically connected by the first conductive particles to a connection terminal or a vertical connection conductor that is exposed from the substrate structure, attaching a second anisotropic conductive film including second conductive particles to a rear surface of the substrate structure; and compressing a second redistribution structure on the rear surface of the substrate structure such that a second redistribution conductor of the second redistribution structure that is exposed is electrically connected by the second conductive particles to the vertical connection conductor.

Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.

An IC chip includes I/O bumps on a back side, a first die, a second die, a first circuit, and a second circuit. The first die has driver circuits for LED devices, the LED devices being located on a front-facing surface of the first die. The first circuit extends from the front side toward the back side and across a thickness of the first die. The first circuit provides electrical connections between the LED devices and at least some of the I/O bumps. The first die and the second die can be stacked vertically or arranged laterally adjacent. The second circuit extends between the first die and the second die to electrically connect the first die and the second die. A circuit board can be electrically connected to the IC chip through the I/O bumps to, among other things, provide power to the various components of the IC chip.

A semiconductor package includes a redistribution substrate including a first redistribution layer, a first molding member on the redistribution substrate, a second redistribution layer on an upper surface of the first molding member and having a redistribution pad, an electrical connection pad on an upper surface of a second molding member and electrically connected to the second redistribution layer, and a passivation layer on the second molding member and having an opening exposing at least a portion of the electrical connection pad. The electrical connection pad includes a conductor layer, including a first metal, and a contact layer on the conductor layer and including a second metal. The redistribution pad includes a third metal, different from the first metal and the second metal. The portion of the electrical connection pad, exposed by the opening, has a width greater than a width of the redistribution pad.