Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and with a top surface of the first through-substrate via; and an interconnect structure including a first dielectric layer and first conductive vias, the first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate, the first conductive vias extending through the first dielectric layer to contact the top surface of the first through-substrate via.

A semiconductor device is disclosed mounted at an angle on a signal carrier medium such as a printed circuit board. The semiconductor device includes a stack of semiconductor die stacked in a stepped offset configuration. The die stack may then be encapsulated in a block of molding compound. The molding compound may then be singulated with slanted cuts along two opposed edges. The slanted edge may then be drilled to expose the electrical contacts on each of the semiconductor die. The slanted edge may then be positioned against a printed circuit board having solder or other conductive bumps so that the conductive bumps engage the semiconductor die electrical contacts in the drilled holes. The device may then be heated to reflow and connect the electrical contacts to the conductive bumps.

A semiconductor memory device includes a substrate that has a first main surface and a second main surface opposite to the first main surface, a first semiconductor chip which is mounted on the first main surface and includes a first register, a plurality of first input/output (IO) terminals, and a first circuit connected between the first IO terminals and the first register, and a second semiconductor chip which is mounted on the second main surface and includes a second register, a plurality of second input/output (IO) terminals, and a second circuit connected between the second IO terminals and the second register. The second circuit is connected to the second IO terminals through input lines and to the second register through output lines, and is configured to change a connection path between the input lines and the output lines in response to a connection change command.

A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.

A semiconductor memory device includes a substrate that has a first main surface and a second main surface opposite to the first main surface, a first semiconductor chip which is mounted on the first main surface and includes a first register, a plurality of first input/output (IO) terminals, and a first circuit connected between the first IO terminals and the first register, and a second semiconductor chip which is mounted on the second main surface and includes a second register, a plurality of second input/output (IO) terminals, and a second circuit connected between the second IO terminals and the second register. The second circuit is connected to the second IO terminals through input lines and to the second register through output lines, and is configured to change a connection path between the input lines and the output lines in response to a connection change command.

A power semiconductor module may include a first plate, a second plate configured to include first and second device receiving portions thereinside, and coupled to one side of the first plate, first and second power semiconductor devices arranged in the first and second device receiving portions, first and second input bus bars coupled to an outside of the second plate, a third plate configured to include third and fourth device receiving portions thereinside, and coupled to the other side of the first plate, third and fourth power semiconductor devices arranged in the third and fourth device receiving portions, and third and fourth input bus bars coupled to an outside of the third plate.

Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an L shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a C shape and include a tiered portion that projects towards the lateral side of the second casing.

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.

A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.