A method of forming a semiconductor package includes receiving a carrier, coating the carrier with a bonding layer, forming a first insulator layer over the bonding layer, forming a backside redistribution layer over the first insulator layer, forming a second insulator layer over the backside redistribution layer, patterning the second insulator layer to form a recess that extends through the second insulator layer and to the backside redistribution layer, filling the recess with a solder, and coupling a surface-mount device (SMD) to the solder.

The semiconductor package including a first semiconductor package including a first semiconductor package substrate, and a first semiconductor chip on the first semiconductor package substrate, an interposer disposed on the first semiconductor package is provided. Interposer electrically connects the first semiconductor package with an external semiconductor package, and has first and second sides opposed to each other. The second side is located between the first side and the first semiconductor package substrate, a first recess is formed in the second side of the interposer. The first recess has side walls extended from the second side toward the first side of the interposer and an upper surface connected to the side walls and the upper surface of the first recess faces the first semiconductor chip and a via in the interposer. The via does not transmit an electrical signal between the first semiconductor package and the external semiconductor package.

In one example, a semiconductor structure comprises a redistribution structure comprising a conductive structure, a cavity substrate on a top side of the redistribution structure and having a cavity and a pillar contacting the redistribution structure, an electronic component on the top surface of the redistribution structure and in the cavity, wherein the electronic component is electrically coupled with the conductive structure, and an encapsulant in the cavity and on the top side of the redistribution structure, contacting a lateral side of the electronic component, a lateral side of the cavity, and a lateral side of the pillar. Other examples and related methods are also disclosed herein.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

A semiconductor package may include a substrate having an upper surface on which a plurality of first pads are disposed and a lower surface on which a plurality of second pads are disposed. The semiconductor package may further include a semiconductor chip disposed on the upper surface of the substrate on which connection electrodes connected to a first set of the plurality of first pads are disposed. The semiconductor package may include an interposer having an upper surface on which a plurality of first connection pads, connected to a second set of the plurality of first pads, and a plurality of second connection pads are disposed. The semiconductor package may further include a plurality of connection terminals disposed on a set of the plurality of second connection pads of the interposer, and a molding material disposed on the upper surface of the substrate.

In one example, a semiconductor structure comprises a redistribution structure comprising a conductive structure, a cavity substrate on a top side of the redistribution structure and having a cavity and a pillar contacting the redistribution structure, an electronic component on the top surface of the redistribution structure and in the cavity, wherein the electronic component is electrically coupled with the conductive structure, and an encapsulant in the cavity and on the top side of the redistribution structure, contacting a lateral side of the electronic component, a lateral side of the cavity, and a lateral side of the pillar. Other examples and related methods are also disclosed herein.

There is disclosed a semiconductor package assembly comprising: a substrate having a top substrate surface and a substrate bottom surface; a first semiconductor die, partially over the substrate and having a die bottom surface having first and second pluralities of I/O pads thereon; a first plurality of localised electrical connection components (LECCs), affixed between the die bottom surface and the substrate top surface and providing electrical connections between the substrate and the first plurality of I/O pads; a second plurality of LECCs, affixed to the substrate bottom surface, and for providing electrical connection between the substrate and a circuit board; wherein the second plurality of I/O pads are arranged for providing electrical connections to a chip-scale-package unit to be affixed to the first semiconductor die by a third plurality of LECCs, and to be positioned in a same horizonal plane as the substrate. Corresponding methods are also disclosed.

A semiconductor package structure includes a first redistribution layer, a second redistribution layer and an interconnecting structure. The first redistribution layer has a first surface and a second surface opposite to each other. The second redistribution layer is disposed over the first surface of the first redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface facing the first surface. The interconnecting structure is disposed between and electrically connected to the first redistribution layer and the second redistribution layer, wherein the interconnecting structure comprises a conductive post and a conductive bump stacked to each other.

The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.