A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

A multilayer composite bonding material for transient liquid phase bonding a semiconductor device to a metal substrate includes thermal stress compensation layers sandwiched between a pair of bonding layers. The thermal stress compensation layers may include a core layer with a first stiffness sandwiched between a pair of outer layers with a second stiffness that is different than the first stiffness such that a graded stiffness extends across a thickness of the thermal stress compensation layers. The thermal stress compensation layers have a melting point above a sintering temperature and the bonding layers have a melting point below the sintering temperature. The graded stiffness across the thickness of the thermal stress compensation layers compensates for thermal contraction mismatch between the semiconductor device and the metal substrate during cooling from the sintering temperature to ambient temperature.

A semiconductor chip includes a front surface and a back surface, a source pad, a drain pad and a gate pad on the front surface; a die pad under the semiconductor chip and bonded to the semiconductor chip; a source lead, electrically connected to the die pad; a drain lead and a gate lead, disposed on a periphery of the die pad; and a sealing resin. A plurality of vias for external connection are formed to connect to the source pad. A first subset of the plurality of vias for external connection is disposed along a first side of the source pad, and a second subset of the plurality of vias for external connection is disposed along a second side of the source pad, wherein the first and second sides are arranged adjacent to each other to form a first edge of the source pad.

A semiconductor device includes an indium gallium nitride layer over an active layer. The semiconductor device further includes an annealed region beneath the indium gallium nitride layer, the annealed region comprising indium atoms driven from the indium gallium nitride layer into the active layer.

A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

A method of fabricating a semiconductor-on-diamond composite substrate, the method comprising: (i) starting with a native semiconductor wafer comprising a native silicon carbide substrate on which a compound semiconductor is disposed; (ii) bonding a silicon carbide carrier substrate to the compound semiconductor; (iii) removing the native silicon carbide substrate; (iv) forming a nucleation layer over the compound semiconductor; (v) growing polycrystalline chemical vapor deposited (CVD) diamond on the nucleation layer to form a composite diamond-compound semiconductor-silicon carbide wafer, and (vi) removing the silicon carbide carrier substrate y laser lift-off to achieve a layered structure comprising the compound semiconductor bonded to the polycrystalline CVD diamond via the nucleation layer, wherein in step (ii) the silicon carbide carrier substrate is bonded to the compound semiconductor via a laser absorption material which absorbs laser light, wherein the laser has a coherence length shorter than a thickness of the silicon carbide carrier substrate.

A power electronics assembly includes a semiconductor device stack having a wide bandgap semiconductor device, a semiconductor cooling chip thermally coupled to the wide bandgap semiconductor device, and a first electrode electrically coupled to the wide bandgap semiconductor device and positioned between the wide bandgap semiconductor device and the semiconductor cooling chip. The semiconductor cooling chip is positioned between a substrate layer and the wide bandgap semiconductor device. The substrate layer includes a substrate inlet port and a substrate outlet port. An integrated fluid channel system extends between the substrate inlet port and the substrate outlet port and includes a substrate fluid inlet channel extending from the substrate inlet port into the substrate layer, a substrate fluid outlet channel extending from the substrate outlet port into the substrate layer, and one or more cooling chip fluid channels extending into the semiconductor cooling chip.

A packaged semiconductor chip includes a power amplifier die including a semiconductor substrate, and an input contact pad, an output contact pad, first and second direct-current (DC) contact pads, one or more transistors having an input coupled to the input contact pad, and an input bias coupling path electrically coupling the first DC contact pad to the second DC contact pad and the input contact pad implemented on the semiconductor substrate. The chip further includes a lead frame having one or more radio-frequency input pins electrically coupled to the input contact pad, one or more radio-frequency output pins electrically coupled to the output contact pad, and first and second input bias pins electrically coupled to the first and second DC contact pads, respectively.

A power electronics assembly having a semiconductor device stack having a wide bandgap semiconductor device, a first electrode electrically coupled the wide bandgap semiconductor device, and a second electrode electrically coupled the wide bandgap semiconductor device. A substrate layer is coupled to the semiconductor device stack such that the first electrode is positioned between the substrate layer and the wide bandgap semiconductor device. The substrate layer includes a substrate inlet port and a substrate outlet port. An integrated fluid channel system extends between the substrate inlet and outlet ports and includes a substrate fluid inlet channel extending from the substrate inlet port into the substrate layer, a substrate fluid outlet channel extending from the substrate outlet port into the substrate layer, and one or more semiconductor fluid channels extending into the wide bandgap semiconductor device in fluid communication with the substrate fluid inlet and outlet channels.

An electronics assembly comprises a semiconductor device having a first device surface and at least one device conductive layer disposed on the first device surface. A cooling structure is coupled to the semiconductor device. The cooling structure comprises a first cooling structure surface and a second cooling structure surface. The second cooling structure surface is opposite from the first cooling structure surface and the first cooling structure surface is coupled to the semiconductor device. One side cooling structure surface is transverse to the respective first and second cooling structure surface. The one side electrode is disposed on the at least one side cooling structure surface in which the at least one side electrode is electrically coupled to the at least one device conductive layer. The cooling structure includes a fluid inlet for receiving a cooling fluid and a fluid outlet for removing the cooling fluid from the cooling structure.