A method of fabricating a semiconductor-on-diamond composite substrate, the method comprising: (i) starting with a native semiconductor wafer comprising a native silicon carbidesubstrate on which a compound semiconductor is disposed; (ii) bonding a silicon carbide carrier substrate to the compound semiconductor; (iii) removing the native silicon carbide substrate; (iv) forming a nucleation layer over the compound semiconductor; (v) growing polycrystalline chemical vapour deposited (CVD) diamond on the nucleation layer to form a composite diamond-compound semiconductor-silicon carbide wafer, and (vi) removing the silicon carbide carrier substrate y laser lift-off to achieve a layered structure comprising the compound semiconductor bonded to the polycrystalline CVD diamond via the nucleation layer, wherein in step (ii) the silicon carbide carrier substrate is bonded to the compound semiconductor via a laser absorption material which absorbs laser light, wherein the laser has a coherence length shorter than a thickness of the silicon carbide carrier substrate.

A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.

An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a pass-through structure coupled to the first side of the insulating substrate. The pass-through structure includes an insulating core, a resistor disposed proximate a top surface of the insulating core, and at least one through-hole structure forming at least one conductive pathway through a thickness of the insulating core. A patterned metallization layer is formed on a second side of the insulating substrate. The patterned metallization layer is electrically coupled to at least one first conductive pad of the semiconductor device and electrically couples at least one second conductive pad of the semiconductor device to a through-hole structure of the at least one through-hole structure through the resistor.

A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.

A transient liquid phase (TLP) composition includes a plurality of first high melting temperature (HMT) particles, a plurality of second HMT particles, and a plurality of low melting temperature (LMT) particles. Each of the plurality of first HMT particles have a core-shell structure with a core formed from a first high HMT material and a shell formed from a second HMT material that is different than the first HMT material. The plurality of second HMT particles are formed from a third HMT material that is different than the second HMT material and the plurality of LMT particles are formed from a LMT material. The LMT particles have a melting temperature less than a TLP sintering temperature of the TLP composition and the first, second, and third HMT materials have a melting point greater than the TLP sintering temperature.

A power electronics assembly having a semiconductor device stack having a wide bandgap semiconductor device, a first electrode electrically coupled the wide bandgap semiconductor device, and a second electrode electrically coupled the wide bandgap semiconductor device. A substrate layer is coupled to the semiconductor device stack such that the first electrode is positioned between the substrate layer and the wide bandgap semiconductor device. The substrate layer includes a substrate inlet port and a substrate outlet port. An integrated fluid channel system extends between the substrate inlet and outlet ports and includes a substrate fluid inlet channel extending from the substrate inlet port into the substrate layer, a substrate fluid outlet channel extending from the substrate outlet port into the substrate layer, and one or more semiconductor fluid channels extending into the wide bandgap semiconductor device in fluid communication with the substrate fluid inlet and outlet channels.

A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.

A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.