Techniques for integrating DC-DC power converters with other on-chip circuitry are provided. In one aspect, an integrated DC-DC power converter includes: a GaN transistor chip having at least one GaN switch formed thereon; an interposer chip, bonded to the GaN transistor chip, having at least one power driver transistor formed thereon; TSVs present in the interposer chip adjacent to the power driver transistor and which connect the power driver transistor to the GaN switch; and an on-chip magnetic inductor formed either on the GaN transistor chip or on the interposer chip. A method of forming a fully integrated DC-DC power converter is also provided.

Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction, each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

An LED device capable of emitting electromagnetic radiation ranging from about 200 nm to 365 nm, the device. The device includes a substrate member, the substrate member being selected from sapphire, silicon, quartz, gallium nitride, gallium aluminum nitride, or others. The device has an active region overlying the substrate region, the active region comprising a light emitting spatial region comprising a p-n junction and characterized by a current crowding feature of electrical current provided in the active region. The light emitting spatial region is characterized by about 1 to 10 microns. The device includes an optical structure spatially disposed separate and apart the light emitting spatial region and is configured to facilitate light extraction from the active region.

A radio frequency (RF) integrated circuit includes a first layer of semiconductor material in which a high electron mobility transfer (HEMT) device is formed. A semiconductor heat spreader substrate supports the first layer of semiconductor material. A pair of matching circuits are electrically connected to the HEMT device, wherein the pair of matching circuits are supported on a semiconductor substrate of a semiconductor material different than the semiconductor material of the first semiconductor heat spreader substrate. The first layer of semiconductor material and the first semiconductor heat spreader substrate have a thickness that is less than a second thickness of the semiconductor substrate supporting the pair of matching circuits.

A semiconductor device includes a substrate, a power device, a protection circuit, a dielectric layer, a drain pad, a source pad, and a gate pad. The power device and the protection circuit are disposed on the substrate. The power device includes a drain electrode, a source electrode, and a gate electrode. The protection circuit has a first terminal electrically connected with the source pad and a second terminal electrically connected with the gate pad. The dielectric layer is disposed on the power device and the protection circuit. The drain pad, the source pad, and the gate pad are disposed on the dielectric layer and respectively electrically connected with the drain electrode, the source electrode, and the gate electrode. At least part of the protection circuit is disposed under the source pad, the gate pad, or the drain pad.

A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a first source pad, and a first drain pad. The source electrode, the drain electrode, and the gate electrode are disposed, on an active region of the active layer. The first insulating layer is disposed on the source electrode, the drain electrode, and the gate electrode. The first source pad and the first drain pad are disposed on the first insulating layer and the active region. The first source pad includes a first source body and a first source branch. The first source branch is electrically connected to the first source body and disposed on the source electrode. The first drain pad includes a first drain body and a first drain branch. The first drain branch is electrically connected to the first drain body and disposed on the drain electrode.

Techniques for integrating DC-DC power converters with other on-chip circuitry are provided. In one aspect, an integrated DC-DC power converter includes: a GaN transistor chip having at least one GaN switch formed thereon; an interposer chip, bonded to the GaN transistor chip, having at least one power driver transistor formed thereon; TSVs present in the interposer chip adjacent to the power driver transistor and which connect the power driver transistor to the GaN switch; and an on-chip magnetic inductor formed either on the GaN transistor chip or on the interposer chip. A method of forming a fully integrated DC-DC power converter is also provided.

In order to produce a power semiconductor module, a circuit carrier is populated with a semiconductor chip and with an electrically conductive contact element. After populating, the semiconductor chip and the contact element are embedded into a dielectric embedding compound, and the contact element is exposed. In addition, an electrically conductive base layer is produced which electrically contacts the exposed contact element and which bears on the embedding compound and the exposed contact element. A prefabricated metal film is applied to the base layer by means of an electrically conductive connection layer.