Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.

Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer, a die disposed in a cavity of the core layer, and an encapsulant disposed in the cavity between the die and a sidewall of the cavity. The package further includes a first patterned conductive layer disposed within the first dielectric layer, a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, a second patterned conductive layer disposed within the second dielectric layer, and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer.

A ceramic substrate according to the present invention includes: a ceramic base material; an electrode pattern formed on the ceramic base material; and at least one spacer arranged in any one of regions in the ceramic base material and the electrode pattern, in which a semiconductor chip is mounted.

A semiconductor device includes: a first electrode terminal; a second electrode terminal; a semiconductor element having an electrode on one surface connected to one surface of the first electrode terminal; a wire that connects an electrode on the other surface of the semiconductor element and the second electrode terminal; and a resin portion formed of an insulator covering the semiconductor element, a part of the second electrode terminal, and the one surface of the first electrode terminal, wherein a chamfered portion is formed on at least one of end portions where the first electrode terminal and the second electrode terminal face each other.

A semiconductor device includes an insulating layer having a first surface and a second surface opposite to the first surface. The semiconductor device includes at least one semiconductor element located on a side of the first surface. The semiconductor device includes a first metal sinter and a second metal sinter. The first metal sinter is in contact with the first surface of the insulating layer and the semiconductor element, and bonds the insulating layer and the semiconductor element. The second metal sinter is in contact with the second surface of the insulating layer.

Provided are a semiconductor device, a busbar, and a power converter that can suppress an increase in the size of the device and in inductance while ensuring insulation performance between terminals. For example, a semiconductor device 1 includes a first terminal 110 projecting from a sealing body 100 along a given direction, and a second terminal 120 adjacent to the first terminal 110 with a space formed between the second terminal 120 and the first terminal 110, the second terminal 120 projecting from the sealing body 100 along a given direction in a direction of projection that is the same as a direction of projection of the first terminal 110. The first terminal 110 has a first exposed part 112 exposed outside the sealing body 100. The second terminal 120 has a second sheathed part 121 projecting from the sealing body 100, the second sheathed part 121 being sheathed with an insulating material, and a second exposed part 122 projecting from the second sheathed part 121, the second exposed part 122 being exposed outside the sealing body 100. A distance D2 along a given direction from a front end 121a of the second sheathed part 121 to the sealing body 100 is longer than a distance D1 along the given direction from a front end 112a of the first exposed part 112 to the sealing body 100.

A semiconductor device includes: semiconductor elements; a package sealing the semiconductor elements and being rectangular in a top view; control terminals protruding from a first side of the package; output terminals protruding from a second side facing the first side of the package; and a recessed portion formed in a third side adjacent to the first side and the second side of the package, wherein a part of the control terminals is disposed at end portions of lead frames, the semiconductor device further includes dummy terminals disposed at other end portions of the lead frames, respectively, the dummy terminals protruding from the recessed portion, and an amount of the protrusion of each of the dummy terminals from the recessed portion is smaller than or equal to 0.75 mm.

A power module includes a plurality of conductive wire groups and a sealing member. The plurality of conductive wire groups each include a first bonded portion and a second bonded portion. A maximum gap between intermediate portions of a pair of conductive wire groups adjacent to each other is larger than a first gap between the first bonded portions of the pair of conductive wire groups adjacent to each other. The maximum gap between the intermediate portions of the pair of conductive wire groups adjacent to each other is larger than a second gap between the second bonded portions of the pair of conductive wire groups adjacent to each other. Therefore, the power module is improved in reliability.

A spring electrode for a press-pack power semiconductor module includes a first electrode in contact with a power semiconductor chip, a second electrode arranged to face the first electrode, and a pressure pad which connects the first electrode and the second electrode and has flexibility in a normal direction of opposing surfaces of the first electrode and the second electrode. The opposing surfaces of the first electrode and the second electrode can be polygons of a pentagon or more, the pressure pad can be a cylindrical conductor or a plurality of wire conductors, and sides of the opposing surface of the first electrode and sides of the opposing surface of the second electrode corresponding to these sides are connected in parallel by the pressure pad.

A semiconductor package assembly includes a carrier with a die attach surface and a contact pad separated from the die attach surface, a semiconductor die mounted on the die attach surface, the semiconductor die having a front side metallization that faces away from the die attach surface, an interconnect ribbon attached to the semiconductor die and the contact pad such that the interconnect ribbon electrically connects the front side metallization to the contact pad, and an electrically insulating encapsulant body that encapsulates the semiconductor die and at least part of the interconnect ribbon. The interconnect ribbon includes a layer stack of a first metal layer and a second layer formed on top of the first metal layer. The first metal layer includes a different metal as the second metal layer. The first metal layer faces the front side metallization.