A hybrid silicon carbide (SiC) device includes a first device structure having a first substrate comprising SiC of a first conductivity type and a first SiC layer of the first conductivity type, where the first SiC layer is formed on a face of the first substrate. The first device structure also includes a second SiC layer of a second conductivity type that is formed on a face of the first SiC layer and a first contact region of the first conductivity type, where the first contact region traverses the second SiC layer and contacts the first SiC. The device also includes a second device structure that is bonded to the first device structure. The second device structure includes a switching device formed on a second substrate and a second contact region that traverses a first terminal region of the switching device and contacts the first contact region.

A heterostructure comprising at least one carbon nanomembrane on top of at least one carbon layer, a method of manufacture of the heterostructure, and an electronic device, a sensor and a diagnostic device comprising the heterostructure. The heterostructure comprises at least one carbon nanomembrane on top of at least one carbon layer, wherein the at least one carbon nanomembrane has a thickness of 0.5 to 5 nm and the heterostructure has a thickness of 1 to 10 nm.

A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact.

A first insulation layer comprising stacked prepreg layers is provided, and a metallic protective layer is formed on the first insulation layer. A first alignment mark is formed on the first insulation layer, and an accommodation cavity is formed in the first insulation layer according to the first alignment mark. A second alignment mark is formed on the first insulation layer according to the first alignment mark. A carrier plate is attached on the first insulation layer through a thermal release tape layer, and the semiconductor device is temporarily fixed on the thermal release tape layer within the accommodation cavity according to the second alignment mark. A semi-cured second insulation layer is placed over the first insulation layer, and the second insulation layer is laminated and cured. A re-distribution layer is formed on the second insulation layer, and the re-distribution layer is electrically connected with the semiconductor device.

Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.

Packaged RF transistor amplifiers are provided that include a flat no-lead overmold package that includes a die pad, a plurality of terminal pads and an overmold encapsulation that at least partially covers the die pad and the terminal pads and an RF transistor amplifier die mounted on the die pad and at least partially covered by the overmold encapsulation. These packaged RF transistor amplifiers may have an output power density of at least 3.0 W/mm.sup.2.

Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second switching device. The electronic modules further include a substrate such as a DBC substrate, which includes an insulating layer between a first metal layer and a second metal layer, and may include multiple layers of DBC substrates stacked over one another. The first metal layer includes a first portion and a second portion isolated from one another by a trench formed through the first metal layer between the two portions. The first and second switching devices are over the first metal layer, a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, and a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, with the capacitor extending over the trench.

According to one embodiment, a high-frequency amplifier includes an active element and an output matching circuit. The active element is provided on a substrate. The active element is configured to amplify a signal having a frequency band. The active element includes a cell region. The output matching circuit is connected to the active element. The output matching circuit includes a wire, a transmission line and an output terminal. The wire includes an input end and an output end. The input end of the wire is connected to an output part of the cell region of the active element. The transmission line is provided on the substrate. The transmission line includes an input part and an output part. The input part of the transmission line is connected to the output end of the wire. The output terminal is provided on the substrate.

An embodiment of a Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and a peaking amplifier die. The RF signal splitter divides an input RF signal into first and second input RF signals, and conveys the first and second input RF signals to first and second splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier die includes one or more second power transistors configured to amplify, along a peaking signal path, the second input RF signal to produce an amplified second RF signal. The carrier and peaking amplifier die are coupled to the substrate so that the RF signal paths through the carrier and peaking amplifier die extend in substantially different (e.g., orthogonal) directions.

An electronic device and a method for producing an electronic device are disclosed. In an embodiment the electronic device includes a first component and a second component and a sinter layer connecting the first component to the second component, the sinter layer comprising a first metal, wherein at least one of the components comprises at least one contact layer which is arranged in direct contact with the sinter layer, which comprises a second metal different from the first metal and which is free of gold.