A display device has a display region and a side region adjacent to the display region and includes a plurality of display units, a plurality of sensing units, a display driver and a sensor driver. The plurality of display units and the plurality of sensing units are disposed in the display region. The display driver is coupled to at least a portion of the plurality of display units, and includes a plurality of first thin-film transistors having a first channel layer. The sensor driver is coupled to at least a portion of the plurality of sensing units, and includes a plurality of second thin-film transistors having a second channel layer. At least a portion of the plurality of first thin-film transistors and at least a portion of the plurality of second thin-film transistors are disposed in the side region.

An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

A semiconductor device package includes a first substrate, a dielectric layer, a thin film transistor (TFT) and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The dielectric layer is disposed on the first surface of the first substrate. The dielectric layer has a first surface facing away from the first substrate and a second surface opposite to the first surface. The TFT layer is disposed on the dielectric layer. The electronic component is disposed on the second surface of the first substrate. A roughness of the first surface of the dielectric layer is less than a roughness of the first surface of the first substrate.

A micro-transfer printable electronic component includes one or more electronic components, such as integrated circuits or LEDs. Each electronic component has device electrical contacts for providing electrical power to the electronic component and a post side. A plurality of electrical conductors includes at least one electrical conductor electrically connected to each of the device electrical contacts. One or more electrically conductive connection posts protrude beyond the post side. Each connection post is electrically connected to at least one of the electrical conductors. Additional connection posts can form electrical jumpers that electrically connect electrical conductors on a destination substrate to which the printable electronic component is micro-transfer printed. The printable electronic component can be a full-color pixel in a display.

A chip package structure including a redistribution structure layer, at least one chip, and an encapsulant is provided. The redistribution structure layer includes at least one redistribution circuit, at least one transistor electrically connected to the redistribution circuit, and a plurality of conductive vias electrically connected to the redistribution circuit and the transistor. The chip is disposed on the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the redistribution structure layer and at least encapsulates the chip. A manufacturing method of a chip package structure is also provided.

A semiconductor device package includes a first substrate, a dielectric layer, a thin film transistor (TFT) and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The dielectric layer is disposed on the first surface of the first substrate. The dielectric layer has a first surface facing away from the first substrate and a second surface opposite to the first surface. The TFT layer is disposed on the dielectric layer. The electronic component is disposed on the second surface of the first substrate. A roughness of the first surface of the dielectric layer is less than a roughness of the first surface of the first substrate.

Embodiments of the present disclosure provide a technique advantageous to an improvement in performance of a semiconductor device. The semiconductor device includes a first monocrystalline semiconductor layer on which a first semiconductor element is arranged, a second monocrystalline semiconductor layer on which a second semiconductor element is arranged, and a thin film transistor electrically connected to the first semiconductor element without an intervention of another semiconductor element arranged on the first monocrystalline semiconductor layer and electrically connected to the second semiconductor element without an intervention of another semiconductor element arranged on the second monocrystalline semiconductor layer.

An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

A display according to various embodiments of the present disclosure may include: a first face oriented in a first direction; a second face oriented in a second direction opposite the first direction; a plurality of pixels disposed in a space between the first face and the second face; and a plurality of pins disposed on the second face and configured to electrically connect the plurality of pixels to an external device. Each of the plurality of pixels may include a plurality of LEDs and a driving circuit, the plurality of LEDs may be disposed in the space such that light-emitting portions thereof face the first face, a conductive pattern configured to electrically connect the plurality of LEDs to the driving circuit may be located in the space, at least a portion of the conductive pattern being located above the plurality of LEDs when viewed from above the second face, and a wiring line configured to electrically connect the driving circuit to the plurality of pins may be located in the space, the wiring line being located above the plurality of LEDs when viewed from above the second face.