A power module apparatus includes a power module having a package configured to seal a perimeter of a semiconductor device, and a heat radiator bonded to one surface of the package; a cooling device having a coolant passage through which coolant water flows, in which the heat radiator is attached to an opening provided on a way of the coolant passage, wherein the heat radiator of the power module is attached to the opening of the cooling device so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating.

A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.

Gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern by gate wires. Sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern by source wires. The gate control pattern is disposed to interpose the source control pattern between the gate control pattern and each of the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. Hence, each of the gate wires becomes longer than each of the source wires, and has an inductance larger than the source wire. Accordingly, gate oscillation is reduced or suppressed in the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel.

To improve yield and reliability at the time when a plurality of semiconductor elements used for a semiconductor device is arranged in parallel. A semiconductor device according to the present invention includes a first submodule which includes a first semiconductor element sandwiched between a first conductor and a second conductor and a first lead wire which transmits a control signal of the first semiconductor element, a second submodule which includes a second semiconductor element sandwiched between a third conductor and a fourth conductor and a second lead wire which transmits a control signal of the second semiconductor element, a fifth conductor which is formed to cover the first conductor and the third conductor and is bonded to the first conductor and the third conductor, and a sixth conductor which is formed to cover the second conductor and the fourth conductor and is bonded to the second conductor and the fourth conductor, in which the first conductor is formed so as not to overlap with a part of the first lead wire facing a first connection portion to be connected to the second lead wire.

A semiconductor module arrangement includes a housing and at least one pair of semiconductor substrates arranged inside the housing. Each pair of semiconductor substrates includes first and second semiconductor substrates. The first semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The second semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The third metallization layer of the first semiconductor substrate is electrically coupled to a first electrical potential, and the third metallization layer of the second semiconductor substrate is electrically coupled to a second electrical potential that is opposite to the first electrical potential.

A circuit arrangement is disclosed herein. The circuit arrangement includes a circuit carrier board, a power semiconductor arranged on the underside of the circuit carrier board, and a wiring carrier board arranged underneath the power semiconductor. The circuit arrangement further includes a metallic first spacer element arranged between the circuit carrier board and the wiring carrier board and via which an electric load current from the power semiconductor flows, wherein the first spacer element acts as a shunt through which current flows. The circuit arrangement further includes a voltage measuring unit, by which a voltage drop across the first spacer element, produced by the load current flow, may be determined. A converter having such a circuit arrangement, an aircraft having a converter, and a method for current measurement in power semiconductors are likewise specified.

A semiconductor apparatus includes a base plate, an adhesive agent provided on an upper face of the base plate, and a casing having a lower face and an inclined face continuous to the lower face and positioned closer to a center of the base plate than the lower face, and fixed to the base plate through the adhesive agent adhering to the lower face and the inclined face, wherein of the adhesive agent, a portion that is in contact with the inclined face is thicker than a portion thereof that is in contact with the lower face.

Use of gallium nitride (GaN) semiconductor material for power devices is challenging due to low yield caused by high defect density on the wafer. Device layout on the wafer, chip probing, and device packaging increase the yield of large area power devices. Device dies containing a plurality of lower-power sub-devices are used to achieve high power ratings, by connecting only functional sub-devices together in the package, while being tolerant of defective sub-devices by selectively excluding the defective sub-devices. The packages and methods are particularly relevant to GaN power switching devices such as high electron mobility transistors (GaN HEMT).

A semiconductor package comprises a lead frame, a first field-effect transistor (FET), a second low side FET, a first high side FET, a second high side FET, a first metal clip, a second metal clip, and a molding encapsulation. The semiconductor package further comprises an optional integrated circuit (IC) controller or an optional inductor. A method for fabricating a semiconductor package. The method comprises the steps of providing a lead frame; attaching a first low side FET, a second low side FET, a first high side FET, and a second high side FET to the lead frame; mounting a first metal clip and a second metal clip; forming a molding encapsulation; and applying a singulation process.

A three-phase switching unit including three identical switching cells, each including a first switch and a second switch electrically in series, including a substrate having: a first level receiving, on conductive areas, back sides of integrated circuits forming said switches; and at least one second level comprising conductive areas of interconnection of vias between the first and second levels, the conductive areas of the different levels respecting a symmetry of revolution of order 3.