A semiconductor device includes a plurality of main terminals extending from one end of a base plate toward the other end thereof, a group of semiconductor chips on a side of higher electric potential disposed on one side of the main terminal and mounted on the base plate, and a group of semiconductor chips on a side of lower electric potential disposed on the other side of the main terminal and mounted on the base plate. The one main terminal has an extending portion extending, in a direction perpendicular to the extending direction of the main terminal, toward one of both sides of the main terminal, and two adjacent semiconductor chips in one of the group of semiconductor chips on the side of higher electric potential and the group of semiconductor chips on the side of lower electric potential are axisymmetrically disposed with respect to the extending portion.

A lead frame has a first sink, an island, and a control terminal. The lead frame is bent, and at a rear surface, the island is positioned closer to one surface of a resin molded body than the first sink and a passive component mounting portion of the control terminal. A passive component is mounted on the passive component mounting portion of the control terminal through a bonding material, the passive component mounting portion being a part of one surface.

There is disclosed herein clock generation circuitry, in particular rotary travelling wave oscillator circuitry. Such circuitry comprises a pair of signal lines connected together to form a closed loop and arranged such that they define at least one transition section where both said lines in a first portion of the pair cross from one lateral side of both said lines in a second portion of the pair to the other lateral side of both said lines in the second portion of the pair.

A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

A semiconductor device includes first and second semiconductor chips mounted on one package. In the first semiconductor chip, a current generation circuit generates a sense current in accordance with a load current and a fault current indicating that an abnormality detection circuit has detected an abnormality, and allows either one of the currents to flow through a current detecting resistor in accordance with presence or absence of detection of the abnormality. In the second semiconductor chip, a storage circuit stores a current value of the fault current obtained in an inspection process of the semiconductor device as a determination reference value. An arithmetic processing circuit sets a standard range based on the determination reference value, and determines presence or absence of detection of the abnormality based on whether or not a current value indicated by a digital signal of an analog-digital conversion circuit is included within the standard range.

A lead frame has a first sink, an island, and a control terminal The lead frame is bent, and at a rear surface, the island is positioned closer to one surface of a resin molded body than the first sink and a passive component mounting portion of the control terminal. A passive component is mounted on the passive component mounting portion of the control terminal through a bonding material, the passive component mounting portion being a part of one surface.

A semiconductor device includes a plurality of main terminals extending from one end of a base plate toward the other end thereof, a group of semiconductor chips on a side of higher electric potential disposed on one side of the main terminal and mounted on the base plate, and a group of semiconductor chips on a side of lower electric potential disposed on the other side of the main terminal and mounted on the base plate. The one main terminal has an extending portion extending, in a direction perpendicular to the extending direction of the main terminal, toward one of both sides of the main terminal, and two adjacent semiconductor chips in one of the group of semiconductor chips on the side of higher electric potential and the group of semiconductor chips on the side of lower electric potential are axisymmetrically disposed with respect to the extending portion.

Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.

An electric package device is provided, including a first chip and a second chip. The first chip includes a first conductive pad. The second chip includes a second conductive pad. The second conductive pad couples to the first conductive pad through a connection wire. In some embodiments, the first chip includes a first signal control circuit that receives, in response to a selection signal, one of multiple input signals as a first signal, filters the first signal, and outputs the filtered first signal, as a second signal, from the first conductive pad to the second conductive pad.

The present disclosure relates to an electronic device that includes a first electronic component, a second electronic component, an interconnection structure below the first electronic component and the second electronic component and electrically connecting the first electronic component to the second electronic component, and a first waveguide below the first electronic component and the second electronic component and configured to transmit electromagnetic waves.