Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a lower semiconductor chip on a first redistribution substrate and including a through via, a lower molding layer on the first redistribution substrate and surrounding the lower semiconductor chip, a lower post on the first redistribution substrate and laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and coupled to the through via, an upper molding layer on the lower molding layer and surrounding the upper semiconductor chip, an upper post on the lower molding layer and laterally spaced apart from the upper semiconductor chip, and a second redistribution substrate on the upper molding layer and coupled to the upper post. A top surface of the lower molding layer is at a level higher than that of a top surface of the lower semiconductor chip.

A semiconductor package comprises a first redistribution layer including a first conductive pattern; a connection module on an upper surface of the first redistribution layer; a glass core extending around the connection module on the upper surface of the first redistribution layer; a through via extended in the glass core; a second insulating layer on the glass core, wherein a portion of the second insulating layer is in the through via; a second redistribution layer on an upper surface of the glass core, wherein the second redistribution layer includes a via pad; and a first semiconductor chip and a second semiconductor chip space apart from each other on an upper surface of the second redistribution layer, wherein the via pad is in contact with the through via, and wherein the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the connection module.

A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.

Provided is a semiconductor package including a first semiconductor device including a first semiconductor substrate, a first interconnect structure on the first semiconductor substrate, and a trench extending into the first interconnect structure and a portion of the first semiconductor substrate, a second semiconductor device on the first semiconductor device, and a cover insulating layer on the first semiconductor device and a side surface of the second semiconductor device, the cover insulating layer including a first portion filling the trench included in the first semiconductor device and contacting the first semiconductor substrate.

A semiconductor package includes a package substrate, an interposer above the package substrate, a connection terminal between the package substrate and the interposer, a first semiconductor chip and a second semiconductor chip above the interposer, a bridge in the interposer, the bridge connected to the first semiconductor chip and the second semiconductor chip, a capacitor structure in the interposer, the capacitor structure including an upper structure including an upper capacitor and a lower structure including a lower capacitor, and a chip connection terminal including at least one first chip connection terminal between the interposer and the first semiconductor chip and at least one second chip connection terminal between the interposer and the second semiconductor chip.

A semiconductor package an interposer disposed on a substrate, a recess recessed from an upper surface of the interposer, a connection structure disposed inside the recess, a first post disposed on the upper surface of the interposer and electrically connected to the interposer, a second post disposed on an upper surface of the connection structure and electrically connected to the connection structure, a first lower semiconductor chip disposed between the first and second posts and disposed on the upper surface of the interposer and the upper surface of the connection structure. The first lower semiconductor chip is electrically connected to the second post through the connection structure, and a first upper semiconductor chip is disposed on an upper surface of the first lower semiconductor chip. The first upper semiconductor chip is electrically connected to the first lower semiconductor chip through the second post and the connection structure.

An electrical device that includes at least two active wafers having at least one through silicon via, and at least one unitary electrical communication and spacer structure present between a set of adjacently stacked active wafers of the at least two active wafers. The unitary electrical communication and spacer structure including an electrically conductive material core providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers and a substrate material outer layer. The at least one unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the at least one unitary electrical communication and spacer structure.

Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs the programmable logic fabric. The programmable logic fabric of the fabric die may access at least a portion of the active interposer to perform an operation. As discussed herein, different power management techniques associated with the active interposer may be used to improve operation of the device.

A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of tire plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.