Wireless modules having a semiconductor package attached to an antenna package and cap package are disclosed. The semiconductor package may have one or more electronic components disposed thereon. The antenna package may be communicatively coupled to the semiconductor package using by one or more coupling pads. The antenna package may further have one or more radiating elements for transmitting and or receiving wireless signals. The cap package may also be attached to the semiconductor package on a side opposing the side on which the antenna package is disposed. The cap package may provide routing and/or additional antenna elements. The cap package may also allow for thermal grease to be dispensed therethrough. The antenna package, the cap package, and the semiconductor package may have dissimilar number of interconnect layers and/or dissimilar materials of construct.

Apparatus and methods for protection against inadvertent programming of fuse cells are provided herein. In certain configurations, a fuse system includes a fuse programming transistor, a cascode transistor, and a fuse cell electrically connected in series between a first pad and a second pad. The fuse system further includes a bias generator that controls an amount of current provided to the fuse cell based on biasing a gate of the fuse programming transistor and a gate of the cascode transistor. The fuse system further includes a fuse protection capacitor electrically connected between the first pad and the gate of the cascode transistor to prevent inadvertent programming of the fuse cell in response to an increase in voltage of the first pad relative to the second pad.

Apparatuses, systems and methods associated with dielectric coatings for printed circuit boards are disclosed herein. In embodiments, a printed circuit board (PCB) includes a substrate, microstrip conductors located on a surface of the substrate, a solder mask covering the surface of the substrate and the microstrip conductors, and a dielectric coating located on the solder mask, the dielectric coating on an opposite side of the solder mask from the microstrip conductors, wherein a thickness of the dielectric coating is selected to cause a ratio of capacitive coupling to self capacitance to be approximately equal to a ratio of inductive coupling to self inductance for each microstrip conductor of the microstrip conductors, where the thickness may be determined based on a specific methodology including simulations. Other embodiments may be described and/or claimed.

An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component.

An electronic component package includes a frame containing a metal or ceramic based material and having a through-hole, an electronic component disposed in the through-hole, an insulating part at least covering upper portions of the frame and the electronic component, a bonding part at least partially disposed between the frame and the insulating part, and a redistribution part disposed at one side of the frame and the electronic component.

Apparatus and methods for protection against inadvertent programming of fuse cells are provided herein. In certain configurations, a fuse system includes a fuse programming transistor, a cascode transistor, and a fuse cell electrically connected in series between a first pad and a second pad. The fuse system further includes a bias generator that controls an amount of current provided to the fuse cell based on biasing a gate of the fuse programming transistor and a gate of the cascode transistor. The fuse system further includes a fuse protection capacitor electrically connected between the first pad and the gate of the cascode transistor to prevent inadvertent programming of the fuse cell in response to an increase in voltage of the first pad relative to the second pad.

A fan-out semiconductor package includes a first connection member having a through-hole, first and second semiconductor chips disposed in the through-hole, an encapsulant encapsulating at least portions of the first connection member, the first semiconductor chip, and the second semiconductor chip, and a second connection member disposed on the first connection member and on active surfaces of the first semiconductor chip and the second semiconductor chip. A redistribution layer of the second connection member is respectively connected to both the first and second connection pads through first and second conductors, and the second conductor has a height greater than that of the first conductor.

A packaged IC includes a fanout layer, an Application Processor (AP) die having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the AP die Process, and high bandwidth memory coupled to a second surface of the RDL and configured to communicate wirelessly with the AP die. The packaged IC further includes an encapsulant surrounding a substantial portion of the high bandwidth memory, the RDL, and the AP die, the encapsulant contacting the fanout layer on a first side and having an exposed second side, a plurality of conductive posts extending from the fanout layer to the RDL through a portion of the encapsulant, and a plurality of Through Mold Vias (TMVs) extending between the fanout layer and the exposed second side of the encapsulant.

An electronic component package includes an electronic component, a redistribution layer electrically connected to the electronic component and having terminal connection pads, a passivation layer disposed on one side of the redistribution layer and having openings exposing at least portions of the terminal connection pads, and connection terminals disposed in the openings of the passivation layer and connected to the terminal connection pads. At least one of the openings of the passivation layer has a plurality of protrusion parts.

A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a first metal layer, a peripheral circuit configured to control the memory cell array, a second metal layer, and a pad. The first metal layer is disposed on the memory cell array and includes a plurality of cell region interconnections connected to the memory cell array. The second metal layer is disposed on the peripheral circuit and includes a plurality of peripheral region interconnections connecting the peripheral circuit and the plurality of cell region interconnections. The pad is disposed on the second metal layer and exchanges data, an address, or a command with the peripheral circuit during operation of the device. The second metal layer is lower than the first metal layer relative to a substrate of the device.