An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.

An electronic component mounting package is provided with a metal substrate including a first surface, a recessed portion opening on the first surface, and a mounting portion for an electronic component in the recessed portion, and a wiring conductor located on the first surface via an insulation layer other than at the opening of the recessed portion, and a metal oxide film is included on at least a part of the inner side surface of the recessed portion.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

A method for light-emitting element transferring includes: providing multiple light-emitting elements, each light-emitting element includes a first light-emitting unit, a substrate, and a second light-emitting unit sequentially stacked, the first light-emitting unit includes a first epitaxial structure and a first electrode group stacked on a side of the substrate, the second light-emitting unit includes a second epitaxial structure and a second electrode group stacked on another side of the substrate, and the first light-emitting unit and the second light-emitting unit have different light-emitting colors; providing a display backplane, multiple grooves are defined on the display backplane, a first pad group and a second pad group are provided on side walls of each groove; and embedding the multiple light-emitting elements into the multiple grooves in one-to-one correspondence, where the first electrode group is bonded with the first pad group, and the second electrode group is bonded with the second pad group.

A package that includes a substrate, an integrated device, a first encapsulation layer and a void. The substrate includes a first surface. The integrated device is coupled to the first surface of the substrate. The first encapsulation layer is located over the first surface of the substrate and the integrated device. The first encapsulation layer includes an undercut relative to a side surface of the integrated device. The void is located between the integrated device and the first surface of the substrate. The void is laterally surrounded by the undercut of the encapsulation layer.

In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device comprising at least one first thermally conductive structure proximate at least one of the first integrated circuit device, the second integrated circuit device, and the substrate; and a second thermally conductive structure disposed over the first thermally conductive structure(s), the first integrated circuit device, and the second integrated circuit device, wherein the first thermally conductive structure(s) have a lower electrical conductivity than an electrical conductivity of the second thermally conductive structure. The first thermally conductive structure(s) may be formed by an additive process or may be pre-formed and attached to at least one of the first integrated circuit device, the second integrated circuit device, and the substrate.

A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer.

An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.

A method for producing a multiplicity of semiconductor chips (13) is provided, comprising the following steps: providing a wafer (1) comprising a multiplicity of semiconductor bodies (2), wherein separating lines (9) are arranged between the semiconductor bodies (2), depositing a contact layer (10) on the wafer (1), wherein the material of the contact layer (10) is chosen from the following group: platinum, rhodium, palladium, gold, and the contact layer (10) has a thickness of between 8 nanometres and 250 nanometres, inclusive, applying; the wafer (1) to a film (11), at least partially severing the wafer (1) in the vertical direction along the separating lines (9) or introducing fracture nuclei (12) into the wafer (1) along the separating lines (9), and breaking the wafer (1) along the separating lines (9) or expanding the film (11) such that a spatial separation of the semiconductor chips (13) takes place, wherein the contact layer (10) is also separated. A semiconductor chip, a component and a method for producing the latter are also provided.