A carrier substrate having a plurality of receptacles each for receiving and carrying a semiconductor chip is provided. Semiconductor chips are arranged in the receptacles, and metal is plated in the receptacles to form a metal structure on and in contact with the semiconductor chips. The carrier substrate is cut to form separate semiconductor devices.

An electronics module assembly is described herein that packages dies using a universal cavity wafer that is independent of electronics module design. In one embodiment, the electronics module assembly can include a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports. The assembly can also include at least one group of dies placed in the frontside cavity and encapsulant that secures the position of the at least one group of dies relative to the cavity wafer. Further, a layer of the encapsulant can cover a backside of the cavity wafer.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

A semiconductor package includes a cavity substrate, a semiconductor die, and an encapsulant. The cavity substrate includes a redistribution structure and a cavity layer on an upper surface of the redistribution structure. The redistribution structure includes pads on the upper surface, a lower surface, and sidewalls adjacent the upper surface and the lower surface. The cavity layer includes an upper surface, a lower surface, sidewalls adjacent the upper surface and the lower surface, and a cavity that exposes pads of the redistribution structure. The semiconductor die is positioned in the cavity. The semiconductor die includes a first surface, a second surface, sidewalls adjacent the first surface and the second surface, and attachment structures that are operatively coupled to the exposed pads. The encapsulant encapsulates the semiconductor die in the cavity and covers sidewalls of the redistribution structure.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

In a described example, an apparatus includes: a first mold compound partially covering a thermal pad that extends through a pre-molded package substrate formed of a first mold compound, a portion of the thermal pad exposed on a die side surface of the pre-molded package substrate, the pre-molded package substrate having a recess on the die side surface, with an exposed portion of the thermal pad and a portion of the first mold compound in a die mounting area in the recess; a semiconductor die mounted to the thermal pad and another semiconductor die mounted to the mold compound in the die mounting area; wire bonds coupling bond pads on the semiconductor dies to traces on the pre-molded package substrate; and a second mold compound over the die side surface of the pre-molded package substrate and covering the wire bonds, the semiconductor dies, the recess, and a portion of the traces.

Disclosed herein are a light emitting device package, a backlight unit, an illumination apparatus, and a method of manufacturing a light emitting device package capable of being used for a display application or an illumination application. The light emitting device package includes: a flip-chip type light emitting device having a first terminal and a second terminal installed therebeneath; a substrate having a first electrode formed at one side of an electrode separating space and a second electrode formed at the other side thereof; a first conductive bonding member installed on the first electrode of the substrate so as to be electrically connected to the first terminal of the light emitting device; a second conductive bonding member installed on the second electrode of the substrate so as to be electrically connected to the second terminal of the light emitting device; a reflection encapsulant molded and installed on the substrate so as to form a reflection cup part reflecting light generated in the light emitting device and filled in the electrode separating space to form an electrode separating part; and a filler filled between the reflection cup part and the first and second conductive bonding members.

Various embodiments relate to a semiconductor package structure. The semiconductor package structure includes a first chip having a first surface and a second surface opposite the first surface. The semiconductor package structure further includes a supporter surrounding an edge of the first chip. The semiconductor package structure further includes a conductive layer disposed over the first surface of the first chip and electrically connected to the first chip. The semiconductor package structure further includes an insulation layer disposed over the first surface of the first chip, wherein the insulation layer extends toward and overlaps the supporter in a vertical projection direction. The semiconductor package structure further includes an encapsulant between the first chip and the supporter and surrounding at least the edge of the first chip.

An electronic component includes a substrate that has a first principal surface and a second principal surface, a chip that includes a mounting surface on which a plurality of terminal electrodes are formed and a non-mounting surface positioned on a side opposite to the mounting surface and that is arranged at the first principal surface of the substrate in a posture in which the mounting surface faces the first principal surface of the substrate, and a sealing resin that seals the chip at the first principal surface of the substrate so as to expose the non-mounting surface of the chip.