A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. The wire bonds can have first portions extending within the reinforcing dielectric layer. The first portions of at least some of the wire bonds can have bends that change an extension direction of the respective wire bond. The reinforcing dielectric layer can have protruding regions surrounding respective ones of the wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions. The peak heights of the protruding regions can coincide with points of contact between the reinforcing dielectric layer and individual wire bonds.

A semiconductor device includes a wiring substrate, a semiconductor element mounted on an upper surface of a wiring substrate, and a magnetic shield arranged above the upper surface of the wiring substrate to cover an upper side of the semiconductor element. The magnetic shield is formed from a soft magnetic material and includes inclined faces that are inclined straight with respect to the upper surface of the wiring substrate at a portion overlapped with the semiconductor element in a plan view.

A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. The wire bonds can have first portions extending within the reinforcing dielectric layer. The first portions of at least some of the wire bonds can have bends that change an extension direction of the respective wire bond. The reinforcing dielectric layer can have protruding regions surrounding respective ones of the wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions. The peak heights of the protruding regions can coincide with points of contact between the reinforcing dielectric layer and individual wire bonds.

A process for a substrate having a component-disposing area is provided, and includes the following steps. A core layer including a first surface, a metallic layer and a component-disposing area is provided. The metallic layer is disposed on the first surface and patterned to form a patterned metallic layer including pads located in the component-disposing area. A first dielectric layer is formed on the first surface and covers the patterned metallic layer. A laser-resistant metallic pattern is formed on the first dielectric layer and surrounds a projection area of the first dielectric layer. A release film is disposed on the projection area and covers a portion of the laser-resistant metallic pattern within the projection area. A second dielectric layer is formed on the first dielectric layer and covers the release film and the laser-resistant metallic pattern. A first open hole and a plurality of second open holes are formed.

Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device.

A substrate includes a base layer, first and second circuit layers both coupled to the base layer, a third circuit layer, a fourth circuit layer and two solder resist layers. The first/second circuit layer defines a first/second opening. The third and fourth circuit layers are located at two sides of the first and second circuit layers. The solder resist layers cover outer faces of the third and fourth circuit layers. Each solder resist layer defines a window. The first opening is deviated from the second opening. The third and fourth circuit layers each have a portion exposed to the window to be a solder pad. The first circuit layer and the third circuit layer have a total thickness no more than that of the second circuit layer and the fourth circuit layer. A chip package with the substrate and a method for manufacturing the substrate are also provided.

An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.