An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.

A semiconductor part includes a resin package and an exposed portion exposed from a bottom surface of the resin package. The exposed portion has a first diagonal line perpendicular to both first and third sides of the package as viewed from the bottom surface. The exposed portion also has a second diagonal line perpendicular to both the second fourth side in the bottom view. A first lead terminal portion opposes the exposed portion and has a first shape in the bottom view. A second lead terminal portion, also opposing the exposed portion, has a second shape in the bottom view. A third lead terminal portion opposing the exposed portion, also has the second shape in the bottom view. A fourth lead terminal portion, similarly opposed to the exposed portion, likewise has the second shape in the bottom view.

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.

A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.

A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.

A semiconductor device package includes a copper lead frame, a copper oxide compound layer and an encapsulant. The copper oxide compound layer is in contact with a surface of the copper lead frame. The copper oxide compound layer includes a copper(II) oxide, and a thickness of the copper oxide compound layer is in a range from about 50 nanometers to about 100 nanometers. The encapsulant is in contact with a surface of the copper oxide compound layer.

A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.

A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.

A vertical power component includes a semiconductor substrate, a first electrode in contact with a lower surface of the substrate, and a second electrode in contact with an upper surface of the substrate. The vertical component is mounted to a metal connection plate via a metal spacer. The metal spacer includes a lower surface soldered to the metal connection plate and an upper surface soldered to the first electrode of the vertical power component. The metal spacer is made of a same metal as the metal connection plate. A surface are of the metal spacer mounted to the first electrode is smaller than a surface area of the first electrode.