Abstract
Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.
Claims
1. Method for manufacturing an electronic semiconductor package, wherein the method comprises: coupling an electronic chip to a carrier; encapsulating the electronic chip at least partially and encapsulating the carrier partially by an encapsulation structure having a discontinuity, wherein side walls of the encapsulation structure surrounding the discontinuity are inclined by an angle in a range of between 5° and 35° with respect to a vertical extension; covering at least a part of the discontinuity and a volume connected thereto, which adjoins an exposed surface section of the carrier, with an electrically insulating thermal interface structure, which electrically decouples at least a part of the carrier with respect to a surrounding.
2. Method in accordance with claim 1, wherein the thermal interface structure for providing a thermal coupling is formed between the carrier and a heat dissipation element, which is connectable to the thermal interface structure.
3. Method in accordance with claim 1, wherein the method comprises a formation of the discontinuity during the encapsulation.
4. Method in accordance with claim 3, wherein the discontinuity is formed by a protrusion, at an encapsulation tool, shaped inversely to the discontinuity, whereby encapsulation material is precluded from flowing into the discontinuity.
5. Method in accordance with claim 1, wherein the discontinuity is formed as a closed, annular discontinuity.
6. Method in accordance with claim 5, wherein the closed, annular discontinuity is formed to surround the exposed surface section of the carrier completely.
7. Method in accordance with claim 1, wherein the carrier is an electric carrier, which is coupled electrically to the electronic chip.
8. Method in accordance with claim 1, wherein the discontinuity is selected from a group consisting of a recess and a furrow.
9. Method in accordance with claim 1, wherein the covering is selected from a group consisting of printing the thermal interface structure onto the discontinuity and onto the connected volume, dispersing material onto the discontinuity and onto the connected volume for forming the thermal interface structure, laminating the thermal interface structure onto the discontinuity and onto the connected volume, form pressing the thermal interface structure onto the discontinuity and onto the connected volume, and immersing at least a part of an external surface of the encapsulated electronic chip and the encapsulated carrier into an at least partially liquid precursor for forming the thermal interface structure.
10. Method in accordance with claim 1, wherein the method comprises a connection of a heat dissipation element with the thermal interface structure.
Description
SHORT DESCRIPTION OF THE FIGURES
(1) Embodiments are illustrated in the figures and are outlined in more detail in the following.
(2) In the figures:
(3) FIG. 1 to FIG. 4 are different cross-sections of respective structures, which are obtained during the implementation of a method for manufacturing an electronic semiconductor package according to an exemplary embodiment, wherein the electronic semiconductor package obtained is depicted in FIG. 4.
(4) FIG. 5 depicts an electronic arrangement according to an exemplary embodiment, which is formed by mounting a heat dissipation element on an electronic semiconductor package produced in accordance with FIG. 4.
(5) FIG. 6 to FIG. 9 are different cross-sections of respective structures, which are obtained during the utilization of a method for manufacturing an electronic semiconductor package in accordance with another exemplary embodiment, wherein the electronic semiconductor package obtained is depicted in FIG. 9.
(6) FIG. 10 depicts an electronic semiconductor in accordance with an exemplary embodiment formed alternately to FIG. 9.
(7) FIG. 11 depicts an electronic arrangement in accordance with another exemplary embodiment, with a double-sided cooling system, which is formed by mounting a heat dissipation element respectively on both sides, on two thermal interface structures formed on the opposing main surfaces of a semiconductor package.
DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS
(8) The same or similar components in the various figures are provided with the same reference numerals.
(9) Before the exemplary embodiments are described with reference to the figures, some general considerations of the exemplary embodiments are outlined:
(10) The adhesion of the thermal interface structure to the component housed by means of the mold structure is often problematic due to the material since, due to the production (in particular, due to the use of an injection molding method), a waxy surface can form on the encapsulation structure. Due to the weakened boundary surface, the reliability of the insulation is limited over the product lifetime of the electronic semiconductor package. The risk of delaminating can affect the dielectric strength of the component since currents from the exterior of the electronic semiconductor package can reach the electric carrier or the electronic chip through the then partially delaminated thermal interface structure and, there, can lead to damage to or the destruction of the component.
(11) In conventional thermal interface structures, the dielectric strength is ensured in that an extended contact surface is utilized. This solution is not practical due to the lack of manageability on the level of the package. A further option is to ensure the insulation by using a single material for the encapsulating compound. Here, the limited thermal performance and heat conductivity of the moldable encapsulating compound is disadvantageous.
(12) In order to overcome these disadvantages, a discontinuity (in particular, in the form of a recess, in the form of a locally limited surface recess or groove, for example) is formed in the encapsulation structure in accordance with an exemplary embodiment, and the discontinuity and an exposed carrier surface are protectively covered against electrical current flow by means of a one-piece thermal interface structure. This extends and complicates the leakage current path and thereby increases the electrical dielectric strength (up to a voltage of 5 kV and higher, for example), wherein, at the same time, an effective protection against undesirable delamination is also achieved, which increases the effective contact surface between the encapsulation structure and the thermal interface structure and thereby the mutually effective adhesive force, by means of the filled recess.
(13) FIG. 1 to FIG. 4 depict different cross-sections of respective structures, which are obtained during the utilization of a method for manufacturing an electronic semiconductor package 400 in accordance with an exemplary embodiment, wherein the electronic semiconductor package 400 obtained in accordance with an exemplary embodiment is depicted in FIG. 4. Thus, in the following, a method for manufacturing the electronic semiconductor package 400 is described.
(14) In order to obtain the structure depicted in FIG. 1, an electronic chip 100, which is designed here in the form of a semiconductor power chip with a vertical current flow in accordance with FIG. 1 to FIG. 5, is first mounted on an electrical carrier 102 in the form of a copper lead frame, by means of, for example, an electrically conductive contact structure 110, for example, a solder, sinter and/or adhesive layer. It is also depicted in FIG. 1 that the electronic chip 100 coupled to the electric carrier 102 by means of wire bonding is additionally electrically coupled by means of a bonding wire 112.
(15) The arrangement thus obtained is then inserted into a cavity 108 of an encapsulation tool 106, in order for this then to undergo an injection molding process. The encapsulation tool 106 has an annular, circumferential protrusion 104 in the interior of the cavity 108.
(16) In order to obtain the structure depicted in FIG. 2, the electronic chip 100 is molded completely and the electrical carrier partially with an encapsulation structure 200, which, due to the presence of the protrusion 104, is produced with a discontinuity 300 depicted in FIG. 3, by means of injecting a fluid casting compound (for example, plastic-based) into the cavity 108 of the encapsulation tool 106. In the exemplary embodiment described, the discontinuity 300 in the form of a furrow is thus produced by a corresponding geometry of the encapsulation tool 106. The annular discontinuity 300 in the encapsulation structure 200 created, depicted only in cross-section in FIG. 3, as can again be seen in FIG. 2, is formed on the encapsulation tool 106 by means of the protrusion 104 formed inversely to the discontinuity 300, whereby a flow of encapsulation material into the discontinuity 300 during the encapsulation is precluded. The initially still fluid casting compound is then cured in order to achieve the complete encapsulation of the electronic chip 100 and the partial encapsulation of the electrical carrier 102. Thus, in the exemplary embodiment described, the discontinuity 300 is formed during the encapsulation process, so that no separate process is required for this.
(17) In order to obtain the structure depicted in FIG. 3, the encapsulation tool 106 is removed after the curing of the encapsulation structure 200. Even though this cannot be seen in the cross-sectional views of FIG. 2 and FIG. 3, the, in this case, annular discontinuity 300 is formed to surround an exposed surface section 302 of the electrical carrier 102 extensively. It can be seen in FIG. 3 that the surface region 302 of the electrical carrier 102 is exposed to its surroundings after removal from the encapsulation tool 106.
(18) It can be seen in the detail 350 of FIG. 3 that the discontinuity 300 has oblique side walls, which are inclined by an angle α, of, for example, 20° with respect to a vertical extension into the encapsulation structure 200. Thus, the adhesion properties of a thermal interface structure 402 to be formed at a later stage can be facilitated on the encapsulation structure 200.
(19) In order to obtain the electronic semiconductor package 400 depicted in FIG. 4, the discontinuity 300 and a volume connected thereto, which adjoins the exposed surface section 302 of the electrical carrier 102, are filled with an electrically insulating and thermally well-conducting thermal interface structure 402 (thermal interface material, TIM), which is formed to provide a thermal coupling between the electrical carrier 102, and a heat dissipation element 500 depicted in FIG. 5. The latter can be connected to the thermal interface structure 402 by the user. Apart from the thermal coupling between the interior of the semiconductor package and the exterior of the semiconductor package, the thermal interface structure 402 simultaneously brings about the electric decoupling and mechanical protection of the electrical carrier 102 and the electronic chip 100 mounted thereon with respect to the semiconductor package exterior. By a variety of processes (pressing, dispersing, laminating, immersing, etc.), the approximately 100 μm to 200 μm thick thermal interface structure 402 or TIM layer in the exemplary embodiment depicted can be mounted so that it fills the furrow in the form of the annular discontinuity 300. The thermal interface structure 402 thus has an entire thickness, D, here, approximately 100 μm to 200 μm, as illustrated in FIG. 4. The thermal interface structure 402 can have a solid body layer of resin with embedded filling particles or, alternately, can be shaped from a formless material (for example, a paste).
(20) FIG. 4 is also a schematic depiction of a leakage current path 410, that is, a current path which an undesirable leakage current must travel, for example, where there is leakage between the material of the encapsulation structure 200 and the thermal interface structure 402, in order to penetrate into the interior of the electronic semiconductor package 400 in an undesirable manner. In this case, the leakage current 410 (or penetrating humidity) can lead to an electrical breakdown and thus damage the electronic components inside the electronic semiconductor package 400, in particular, the electronic chip 100. It can be seen from the form and the length of the leakage current path 410 that, by forming the discontinuity 300 in the encapsulation structure 200 and filling the same with thermal interface structure 402 material, the effective length of the leakage current path 410 is increased prior to triggering undesirable effects in the interior of the electronic semiconductor package 400 in accordance with the exemplary embodiment described, so that, even in the unlikely case of a delamination of the thermal interface structure 402 from the encapsulation structure 200 or the surface section 302 of the electrical carrier 102, the electrical dielectric strength is increased. At the same time, however, the usually critical adhesion of the thermal interface structure 402 to the encapsulation structure 200 is also improved by filling the discontinuity 300 with thermal interface structure 402 material by, on the one hand, increasing the contact surface between these two components and, on the other hand, by bringing about an additional mechanical interlocking, increasing the adhesion.
(21) In order to obtain the electronic arrangement 502 depicted in FIG. 5, a heat dissipation element (heat sink) is directly thermally and mechanically connected to the thermal interface structure 402. FIG. 5 thus depicts the electronic arrangement 502 in accordance with an exemplary embodiment, which is formed by mounting the heat dissipation element 500 on an electronic semiconductor package 400 produced in accordance with FIG. 4. The heat dissipation element 500, as a heat sink, can be connected by the customer. According to FIG. 5, the heat dissipation element 500 is designed as a connection plate 504 made from a single material, for example, from copper, from which multiple spaced heat dissipation fins 506 extend. The connection plate 504 serves as a coupling surface with the thermal interface structure 402. The heat dissipation fins 506 have a large effective surface, which is conducive to an effective thermal balance with the surroundings.
(22) FIG. 6 to FIG. 9 depict different cross-sections of respective structures, which are obtained during the utilization of another method for manufacturing an electronic semiconductor package 400 in accordance with an exemplary embodiment, wherein the electronic semiconductor package 400 obtained is depicted in FIG. 9. The alternate production method described with reference to FIG. 6 to FIG. 9 differs from the method previously described in that the formation of the discontinuity 300 only starts after the completion of the encapsulation of the electronic chip 100 and of the electrical carrier 102 with the casting compound of the encapsulation structure 200.
(23) In order to obtain the structure depicted in FIG. 6, a process as described with reference to FIG. 1 to FIG. 3 is undertaken, with the difference that, in this case, the encapsulation tool 106 is free of the protrusions 104.
(24) Instead, as can be seen in FIG. 6 and FIG. 7, the discontinuity 300 is now formed by removing previously cast encapsulation structure 200 material after the encapsulation structure 200 material has cured. For this, as indicated schematically by the arrows 600 in FIG. 6, the encapsulation structure 200 material is removed using a laser, by means of “laser grooving” or “laser roughening” (or alternately, chemically, for example, by means of etching, or mechanically, for example, by means of grinding). According to the exemplary embodiment depicted, then, the furrow is produced by means of a laser. The annular discontinuity 300 is thus formed by removing material from the encapsulation structure 200, wherein the electrical carrier 102 functions as a removal stop as the material is removed (see FIG. 7). The electrical carrier 102, which is formed of copper, for example, thereby resists the impact of the laser without any appreciable material removal, so that the depth of the discontinuity 300 formed in the exemplary embodiment depicted can be defined particularly precisely. If the electrical carrier 102 functions as a removal stop, then, unlike in accordance with FIG. 3, the discontinuity 300 subsequently directly adjoins the electrical carrier 102. The thermal interface structure 402 then also directly adjoins the electrical carrier 102 after its formation.
(25) As an additional advantage of this embodiment, the surface roughening of the material of the encapsulation structure 200 brought about by the material removal can be viewed as achieving an improved adhesion, as is described in the following with reference to the detail 250 depicted in FIG. 7. Due to the injection molding production method, a surface of the encapsulation structure 200 outside the discontinuity 300 has a waxy surface layer 700, to which the thermal interface structure 402 adheres only moderately. In order to improve the adhesion properties of the encapsulation structure 200 locally, the method comprises the removal of material from the encapsulation structure 200 down to a depth, d (of, for example, at least 10 μm), so that the waxy surface layer 700 is removed locally at the site of the discontinuity 300. The discontinuity 300 is then also delimited by a grainy or rough wall 702 of the encapsulation structure 200, which is formed by filling particles 704 (as a precursor component for forming the encapsulation structure 200).
(26) The thermal interface structure 402 can be applied after the formation of the discontinuity 300 by means of material removal while exposing the grainy material in the region of the filling particles 704 with good adhesion properties, as described above with reference to FIG. 4, in order to obtain the electronic semiconductor package 400 in accordance with the exemplary embodiment described.
(27) FIG. 8 is a schematic depiction of a plan view of the electronic semiconductor package 400. The closed annular enclosure of, in this case, two discontinuities 300, which then has to be filled with the thermal interface structure 402, can be seen in FIG. 8.
(28) A first annular discontinuity 300 forms an enclosure adjoining an outer periphery of the encapsulation structure 200. Additionally, a second annular discontinuity 300 is depicted in FIG. 8, which forms an enclosure adjoining an outer periphery of the electronic chip 100.
(29) In the embodiment depicted in FIG. 8, an annular closure, in particular, of the external discontinuity 300 and, consequently, of the protrusion of the thermal interface structure 402, is not absolutely necessary. In an upper region according to FIG. 8, the clearance between the electronic chip 100 and the discontinuity 300 is particularly small, so that a penetration of current is particularly critical at this location. In contrast, in a lower region according to FIG. 8, the distance between the electronic chip 100 and the discontinuity 300 is larger, so that a penetration of a current is less critical here. Thus, the discontinuity 300 and its filling can be optionally omitted in this lower region and both of these can be limited to the critical regions.
(30) FIG. 9 is a cross-sectional view of the finished electronic semiconductor package 400 with a thermal interface structure 402 in situ. A fastening element 900, depicted in the exemplary embodiment as a screw, can be used for an even better mechanical connection of the individual components of the electronic semiconductor package 400 as a whole with a heat dissipation element 500 as depicted in FIG. 9.
(31) FIG. 10 depicts an electronic semiconductor package 400 formed alternately to FIG. 9, in accordance with an exemplary embodiment, wherein the fastening element 900 is formed as a spring-like clamp, which is fastened to the heat dissipation element 500 by means of a fastening screw.
(32) Instead of connecting the semiconductor package 400 and the heat dissipation element 500 by means of a fastening element 900 (see FIG. 9 and FIG. 10), the heat dissipation element 500 can also be formed as a heat sink on the thermal interface structure 402, by means of a molding method.
(33) FIG. 11 depicts an electronic arrangement 502 in accordance with another exemplary embodiment, with a double-sided cooling system, which is formed by mounting a heat dissipation element 500 respectively on both sides, on two thermal interface structures 402 formed on the opposing main surfaces of a semiconductor package 400. Thus, the thermal interface structures 402 are created here in the form of two discontinuous sections.
(34) In the exemplary embodiment depicted in FIG. 11, the electronic chip 100 is extensively electrically and mechanically connected to a respective electrical carrier 102 on its two opposing main surfaces, by means of bonding. In accordance with FIG. 11, the two electrical carriers 102 sandwiching the electronic chip 100 are formed as two lead frames. As depicted in FIG. 11, the electronic chip 100 and the electrical carriers 102 are encapsulated, in this case, by means of molding, which forms an encapsulation structure 200. Thereby, a first section of one of the electrical carriers 102 is covered by the encapsulation structure 200, while a second section of this electrical carrier 102 protrudes from the encapsulation structure 200 in order to connect to an electronic periphery (not depicted). The other electrical carrier 102 is coupled to the previously described electrical carrier 102 in the interior of the encapsulation structure 200.
(35) As depicted in FIG. 11, the discontinuities 104 are formed here as steps. These steps also bring about an increase in the effective fastening surface between the encapsulation structure 200 and, in this case, two separate thermal interface structures 402, which, on the one hand, improves the mechanical fastening properties and, on the other hand, improves the reliability of the electrical insulation.
(36) Since thermal interface structures 402 are provided on both opposing main surfaces (comprising the steps) of the encapsulation structure 200 and on exposed surface sections of a respective electrical carrier 102, a respective heat dissipation element 500 can also be mounted on each of the interface structures 402. Double-sided cooling is thus achieved. The heat dissipation element 500 can be formed from, for example, aluminum, copper, or a good heat-conductive ceramic material.
(37) For example, a cooling fluid (such as water or air) can flow along or be guided along the heat dissipation elements 500, whereby a thermal exchange is facilitated, and thus heat can be very efficiently dissipated. Of course, other configurations of the heat dissipation element are also possible.
(38) Additionally, it should be noted that “comprising” does not exclude any other elements or steps and that “one” or “a” does not exclude more than one. It should further be pointed out that characteristics or steps which have been described with reference to one of the above exemplary embodiments can also be used in combination with other characteristics or steps of the other exemplary embodiments described above. Reference numerals in the claims should not be viewed as limiting.
