Disclosed herein is a charge pump architecture in which boosting capacitors of adjacent stages are connected only by NMOS type transistors and comprising a first stage receiving a first voltage and outputting an internal voltage; a second stage receiving the internal voltage and outputting a second voltage at an output terminal, and an auxiliary stage connected to the output terminal, the first stage and second stage including a first type of MOS transistors transferring the voltage from input node internal boosting nodes and being cross-coupled; a second type of MOS transistors with their gate biased by a third type of MOS transistors and fourth type of MOS transistors; the third type of MOS transistors connecting the gate of the second type of MOS transistors; and the fourth type of MOS transistors connecting the gate of the second type of MOS transistors

A charge pump includes first and second multiplier stages including first and second capacitor in series with an input node, a final multiplier stage including an output capacitor in series with the second capacitor and an output node, and pre-charge circuitry. The pre-charge circuitry is configured to charge the output capacitor to a first level during an initial phase of a charging operation, wherein the first level is equal to a supply voltage of the data storage system, and decouple a charging path of the pre-charge circuitry from the output capacitor in response to the output capacitor being charged to the first level. The first and second multiplier stages are configured to increase the charge of the output capacitor to second and third levels higher than the first level during second and third phases of the charging operation.

Disclosed herein is a charge pump architecture in which boosting capacitors of adjacent stages are connected only by NMOS type transistors and comprising a first stage receiving a first voltage and outputting an internal voltage; a second stage receiving the internal voltage and outputting a second voltage at an output terminal, and an auxiliary stage connected to the output terminal, the first stage and second stage including a first type of MOS transistors transferring the voltage from input node internal boosting nodes and being cross-coupled; a second type of MOS transistors with their gate biased by a third type of MOS transistors and fourth type of MOS transistors; the third type of MOS transistors connecting the gate of the second type of MOS transistors; and the fourth type of MOS transistors connecting the gate of the second type of MOS transistors.

A boost converter includes a clock generator, a switching converter, a hysteretic controller, and a power tracking module. The clock generator configured to output a clock signal; The switching converter configured to operate at a frequency based on the clock signal. The hysteretic controller configured to regulate an intermediate output from the switching converter. The power tracking module configured to change a frequency control signal that is sent to the clock generator, the change in frequency is based on a current flowing into an output capacitor such that a charge time of the capacitor is minimized when the current is maximized.

During its first and second residence times, corresponding first and second currents flow between a charge pump and a circuit that connects to one of the charge pump's terminals. Based on a feedback measurement from the charge pump, a controller adjusts these first and second currents.

A voltage generation system might include a selectively-enabled resistive voltage divider having a first resistor connected between an output of the voltage generation system and a first feedback node and having a second resistor connected between the first feedback node and a first voltage node; a selectively-enabled capacitive voltage divider having a first capacitor connected between the output and a second feedback node and having a second capacitor connected between the second feedback node and the first voltage node; a comparator having a first input connected to the second feedback node, having a second input connected to a control signal node, and having an output; and a voltage generation circuit configured to generate a voltage level at the output responsive to a logic level of the output of the comparator and to a clock signal; wherein the first feedback node is selectively connected to the second feedback node.

A charge pump generates an output voltage. A first circuit generates a pulse width-modulated signal as a function of a deviation between the output voltage and a setpoint voltage. A second circuit receives a periodic signal and conditions the supply of the periodic signal to a control input of the charge pump as a function of the state of the pulse width-modulated signal.

A high voltage generating circuitry includes a charge-pump and control loop; the control loop includes a voltage divider which receives a high voltage and provides a divided high voltage output. A first circuit element provides a first voltage difference signal. A controller generates a feedback signal based on the first voltage difference signal. An oscillator generates clock signals for operating the charge-pump circuitry, with the frequency of the clock signals being controlled with a control signal. A feedforward path with a second circuit element combines a second reference voltage and a second voltage generated by inverting the supply voltage for obtaining a second voltage difference signal. A third circuit element generates a feedforward compensation signal inversely proportional to a voltage difference between the supply voltage and the second reference voltage. A fourth circuit element generates the control signal by summing the feedback signal and the feedforward compensation signal.

A charge pump circuit is provided, comprising: a first charge pump having an input terminal for receiving a supply voltage and configured to boost the received supply voltage to provide at an output terminal of the first charge pump a first charge pump voltage; a second charge pump having an input terminal coupled to the output terminal of the first charge pump for receiving the first charge pump voltage and configured to boost the received first charge pump voltage to provide at an output terminal of the second charge pump a second charge pump voltage, and a voltage drop sensing device configured to detect drops in the first charge pump voltage and to deactivate second transistors of bypass units associated to the disabled charge pump stages when a drop in the first charge pump voltage is detected.

A charge pump circuit arrangement includes a multitude of capacitors of a first and a second group controlled by non-overlapping clock pulses. The capacitors are partly realized in a semiconductor substrate including a deep well doping region and a high voltage doping region surrounded by the deep well doping region. Switches are connected to a pair of capacitors to control the deep well doping regions with signals in phase with the corresponding clock signal.