Circuits and methods for improved clock signal level shifting in charge pumps that avoids shoot-through current and loss due to simultaneous switching, which may be powered by V.sub.IN or any available level of V.sub.DD, and which provides a high level of clock signal voltage swing. Embodiments include a non-overlapping clock generator that generates a set of separate non-overlapping clock signals that are applied to a differential clock level translator coupled to a charge pump. The differential clock level translator level shifts the set of non-overlapping clock signals to a set of level-shifted non-overlapping clock signals. The charge pump is configured to receive the sets of non-overlapping clock signals and apply them to corresponding NMOS and PMOS switches. The set of level-shifted non-overlapping clock signals have shifted voltages sufficient to switch corresponding switches having elevated source voltages V.sub.S. The charge pump may be a differential charge pump in some embodiments.

Various embodiments of a fault detector for a voltage converter are described. In one example embodiment, briefly, the fault detector is capable to detect one or more fault events during operation of a voltage converter. Likewise, the fault detector is capable to generate one or more fault signals with respect to the one or more to be detected fault events.

Various embodiments of charge adjustment techniques for a switched capacitor power converter are described. In one example embodiment, briefly, charge adjustment techniques may include a technique to control operation of a charge pump for a switched capacitor power converter so that the charge pump is able to adjust the charge of a selected one or more of the two or more charge pump capacitors along a charge transfer path, independent of the charge of other charge pump capacitors of the two or more charge pump capacitors. Likewise, in some instances, a charge may be adjusted in a manner that is to include at least one of the following: a current source, a voltage regulator, an adjustment of switching frequency of a charge pump, a time-based charge operation, a bypass switch with respect to at least one charge pump capacitor, on-resistance modulation for one or more switches of the charge pump, or any combination thereof.

An apparatus for providing electric power to a load includes a power converter that accepts electric power in a first form and provides electric power in a second form. The power converter comprises a control system, a first stage, and a second stage in series. The first stage accepts electric power in the first form. The control system controls operation of the first and second stage. The first stage is either a switching network or a regulating network. The second stage is a regulating circuit when the first stage is a switching network, and a switching network otherwise.

A boost converter includes a clock generator, a switching converter, a hysteretic controller, and a power tracking module. The clock generator configured to output a clock signal; The switching converter configured to operate at a frequency based on the clock signal. The hysteretic controller configured to regulate an intermediate output from the switching converter. The power tracking module configured to change a frequency control signal that is sent to the clock generator, the change in frequency is based on a current flowing into an output capacitor such that a charge time of the capacitor is minimized when the current is maximized.

A power converter circuit included in a computer system may include multiple switched-capacitor circuits that may each be configured to generate a particular voltage level on a regulated power supply node according to a corresponding conversion ratio. A control circuit may, in response to detection of a regulation event, sequentially change the conversion ratios of the multiple-switched capacitor circuits.

A gate driving circuit for a charge pump with slowed rates of current change for reduced EMI emissions includes at least one gate driving sub-circuit. Each gate driving sub-circuit includes a first current mirror, a first PMOS transistor, a first NMOS transistor, and a second current mirror. Gates of the first PMOS transistor and the first NMOS transistor receive a clock signal. Drains of the first PMOS transistor and the first NMOS transistor output a driving signal. When the first PMOS transistor is turned on, the first current mirror provides a charging current. When the first NMOS transistor is turned on, the second current mirror provides a discharge current.

During its first and second residence times, corresponding first and second currents flow between a charge pump and a circuit that connects to one of the charge pump's terminals. Based on a feedback measurement from the charge pump, a controller adjusts these first and second currents.

The elementary pumping cell comprises an input (E) receiving an input voltage (Vin), a clock terminal (H) receiving a first clock signal (CK1) and an output (S), a first capacitor (C1) having a first terminal connected to the clock terminal and a second terminal, a first transistor (A1) having a first source/drain terminal coupled to the input, a second source/drain terminal and a gate terminal, a second transistor (A2) having a first source/drain terminal, a second source/drain terminal coupled to the input and a gate terminal coupled to the second terminal of the first capacitor, a third transistor (A3) having a first source/drain terminal coupled to the first source/drain terminal of the second transistor, a second source/drain terminal coupled to the gate terminal of the second transistor and a gate terminal coupled to the input, and a fourth transistor (A4) having a first source/drain terminal coupled to the second source/drain terminal of the first transistor, a second source/drain terminal coupled to the first source/drain terminal of the second and third transistors and a gate terminal coupled to the input. The gate terminal of the first transistor is coupled to the gate terminal of the second transistor.

A cascade multiplier includes a switch network having switching elements, a phase pump, and a network of pump capacitors coupled with the phase pump and to the switch network. The network of pump capacitors includes first and second capacitors, both of which have one terminal DC coupled with the phase pump, and a third capacitor coupled with the phase pump through the first capacitor.