The charge transfer transistors of a positive or negative charge pump are biased at their gate terminals with a control voltage that provides for an higher level of gate-to-source voltage in order to reduce switch resistance in passing a boosted (positive or negative) voltage to a voltage output of the charge pump. This control voltage is generated using a bootstrapping circuit whose polarity of operation (i.e., negative or positive) is opposite to a polarity (i.e., positive or negative) of the charge pump.

In an embodiment a low-pass filter arrangement has an input terminal for receiving an input voltage, a first voltage source coupled to the input terminal, a serial connection comprising a first and a second filter diode, the serial connection being coupled to the first voltage source, wherein a connection point between the first and the second filter diode is coupled to an output terminal of the filter arrangement, and a first filter capacitor coupled between the output terminal and a filter reference potential terminal. Therein the first voltage source is adapted to provide a first adjustable forward voltage whereby the first and the second filter diodes are both biased in a forward direction.

A charge pump circuit is provided. The charge pump circuit includes a dual-phase charge pump, a first load switch, a second load switch, and a control circuit. The dual-phase charge pump performs a voltage pumping operation on a power source in response to a first clock and a second clock to generate a first pumping voltage at a first node and a second pumping voltage at a second node. The control circuit controls the first load switch in response to a third clock and controls the second load switch in response to a fourth clock. In a period during which the first load switch is turned off, the second load switch transfers the first pumping voltage to an output terminal of the charge pump circuit. In a period during which the second load switch is turned off, the first load switch transfers the second pumping voltage to the output terminal.

A charge pump circuit of a semiconductor memory device, which may include a first pumping stage that includes a first pumping capacitor and a second pumping capacitor, a first transfer stage that transfers a voltage of the first pumping capacitor when a clock signal is at a high level or transfers a voltage of the second pumping capacitor when a inverse clock signal is at the high level, a second pumping stage that includes a third pumping capacitor and a fourth pumping capacitor, and a second transfer stage that transfers a voltage of the third pumping capacitor when the clock signal is at the high level or transfers a voltage of the fourth pumping capacitor when the inverse clock signal is at the high level. The second transfer stage may output multiple times of the input voltage.

The charge transfer transistors of a positive or negative charge pump are biased at their gate terminals with a control voltage that provides for an higher level of gate-to-source voltage in order to reduce switch resistance in passing a boosted (positive or negative) voltage to a voltage output of the charge pump. This control voltage is generated using a bootstrapping circuit whose polarity of operation (i.e., negative or positive) is opposite to a polarity (i.e., positive or negative) of the charge pump.

A charge pump generates an output voltage. A first circuit generates a pulse width-modulated signal as a function of a deviation between the output voltage and a setpoint voltage. A second circuit receives a periodic signal and conditions the supply of the periodic signal to a control input of the charge pump as a function of the state of the pulse width-modulated signal.

An electronic device includes: a clock booster configured to generate a boosted intermediate voltage greater than a source voltage, wherein the clock booster includes: a controller capacitor configured to store energy for providing a control signal, wherein the control signal is for controlling charging operations to generate the boosted intermediate voltage based on the source voltage, and a booster capacitor configured to store energy according to the control signal for providing the boosted intermediate voltage; and a secondary booster operatively coupled to the clock booster, the secondary booster configured to generate an output voltage based on the boosted intermediate voltage, wherein the output voltage is greater than both the source voltage and the boosted intermediate voltage.

A circuit includes a current controller oscillator generating a CCO output signal at a CCO output, a charge pump boosting a supply voltage based on the CCO output signal and producing a charge pump output voltage at an output, and a current sensing circuit sensing load current at the output and generating a feedback signal having a magnitude that varies with the sensed load current if a magnitude of the sensed load current is between lower and upper load current thresholds. A frequency of the CCO output signal is constant at a lower frequency threshold where the sensed load current is below the lower load current threshold, asymptomically rises to an upper frequency threshold where the sensed load current is above the upper load current threshold, and is proportional to the feedback signal where the sensed load current is between the lower and upper load current thresholds.

A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between a ground and positive supply voltage, the intermediate node generating a first signal oscillating between a first and second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between first and third voltages. A CMOS switching circuit includes a first transistor having a source coupled to an input, a second transistor having a source coupled to an output and a gate coupled to receive the second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive the first clock signal. When positively pumping, the first voltage is twice the second voltage and the third voltage is ground. When negatively pumping, the first and third voltages are of opposite polarity and the second voltage is ground.

Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.