A boost converter control method includes: obtaining a peak current reference signal; obtaining a current sense signal; obtaining a flying capacitor (C.sub.FLY) voltage error feedback signal; and providing switch control signals during a peak current limit mode responsive to the peak current reference signal, the current sense signal, and the C.sub.FLY voltage error feedback signal.

An electronic device includes: a clock booster configured to generate a boosted intermediate voltage greater than a source voltage, wherein the clock booster includes: a controller capacitor configured to store energy for providing a gate signal, wherein the gate signal is for controlling charging operations to generate the boosted intermediate voltage based on the source voltage, and a booster capacitor configured to store energy according to the gate signal for providing the boosted intermediate voltage, wherein the booster capacitor has greater capacitance level than the controller capacitor; and a secondary booster operatively coupled to the clock booster, the secondary booster configured to generate an output voltage based on the boosted intermediate voltage, wherein the output voltage is greater than both the source voltage and the boosted intermediate voltage.

A drive device for driving a load includes: an inverter unit having an upper arm element and a lower arm element and converting electric power supplied to the load; and a charge pump circuit that supplies a gate voltage to the upper arm element. An output voltage of the charge pump circuit is variable according to an inverter input voltage input from an inverter input wiring to a high potential side of the inverter unit.

According to some implementation, a charge pump includes a boost charge pump circuit and a buck charge pump circuit sharing a common flying capacitance. In some implementations, the boost pump circuit includes an input node and a boosted-voltage output node, and the buck charge pump circuit includes the input node and a divided-voltage output node. In some implementations, the charge pump of claim 3 wherein the boosted-voltage includes 2Vin, and the divided-voltage includes Vin/2, Vin being an input voltage at the input node. In some implementations, the boost pump circuit further includes a first holding capacitance that couples the boosted-voltage output node to a ground. In some implementations, the buck pump circuit further includes a second holding capacitance that couples the divided-voltage output node to the ground.

The present invention provides a voltage scaling-up circuit which comprises a charge pump circuit and a multiplexer circuit. The charge pump circuit which includes at least one pumping switch, and is configured to operably periodically converts an input voltage to a pumped voltage onto a pump output node through the at least one pumping switch by charging and pumping, such that the pumped voltage has a scaling factor over the input voltage, wherein the at least one pumping switch has a bulk. The multiplexer circuit senses a predetermined voltage and the pumped voltage and selects one of the predetermined voltage and the pumped voltage which has a higher magnitude as a scaled output voltage at a scaled output node; wherein the bulk of the at least one pumping switch is biased to the scaled output voltage.

A fingerprint sensing system comprising a device connection interface including a device reference potential input, a sensing arrangement, and sensing reference potential providing circuitry. The sensing arrangement includes multiple sensing structures and read-out circuitry connected to each of the sensing structures. The sensing reference potential providing circuitry provides a sensing reference potential to the sensing arrangement in the form of a sensing reference signal alternating between a first sensing reference potential and a second sensing reference potential, and comprises a first capacitor; a second capacitor; charging circuitry; and switching circuitry for alternatingly switching the sensing reference potential providing circuitry between a first state in which the first capacitor and the second capacitor are connected in parallel to the charging circuitry; and a second state in which the first capacitor and the second capacitor, when charged, are connected in series between the device reference potential input and the sensing arrangement.

The charge pump circuit includes multiple boosting stages, and each stage includes following units. A first switch circuit is controlled by a first clock signal to couple a second terminal of a first capacitor to a first input terminal or a second input terminal. A third switch circuit is controlled by a second clock signal to couple a second terminal of a second capacitor to the first input terminal or the second input terminal. A second switch circuit is controlled by electric potentials on the second capacitor to couple a first terminal of the first capacitor to the first input terminal or an output terminal. The fourth switch circuit is controlled by electric potentials on the first capacitor to couple a first terminal of the second capacitor to the first input terminal or the output terminal.

A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

A secondary side controller for a switched mode power supply, the controller comprising a first semiconductor die comprising an integrated circuit configured to provide a load connection signal; a second semiconductor die, packaged with the first semiconductor die, comprising a charge pump configured to, in response to the load connection signal received from the integrated circuit of the first semiconductor die, provide a switch signal for control of a load connection switch that controls whether or not the switched mode power supply is electrically connected to a load; wherein the presence or absence of the load connection signal is configured to control whether or not the charge pump generates the switch signal and the amplitude of the load connection signal is configured to control the voltage of the switch signal.

Methods of operating voltage generation circuits include applying a clock signal to a first electrode of a first capacitance having a second electrode connected to a first node of a first current path, applying the clock signal to a second capacitance having a second electrode connected to a gate of a second current path connected in parallel with the first current path and with the second electrode further connected to a first end of a resistance having a second end connected to the second node, passing charge across at least one of the first current path and the second current path while the clock signal has a first logic phase, and mitigating current flow across the first current path and the second current path while the clock signal has a second logic phase opposite the first logic phase, as well as apparatus facilitating such methods.