A control circuit for a power factor correction (PFC) circuit, the control circuit includes a multiplier having first, second, and third multiplier inputs and a multiplier output. The control circuit has an adder having first and second inputs and an output. The first input of the adder is coupled to the multiplier output. The control circuit further includes a root mean square (RMS) calculation circuit configured to determine a square of a root mean square of an input sinusoidal voltage. The RMS calculation circuit has an output coupled to the second multiplier input. An input voltage square calculation circuit is configured to determine a square of the input sinusoidal voltage. The input voltage square calculation circuit has an output coupled to the third multiplier input.

In an example, a current estimating circuit includes a current estimating resistor coupled in series with a current estimating capacitor. The current estimating resistor and the current estimating capacitor are configured to provide a voltage across the current estimating capacitor during a first portion of a switching cycle, in which the voltage across the current estimating capacitor is proportional to an inductor current that flows through an inductor. The current estimating circuit includes a sense resistor configured to provide a sensed voltage across the sense resistor during a second portion of the switching cycle. The current estimating circuit includes a switch configured to apply the sensed voltage to the current estimating capacitor to provide the voltage across the current estimating capacitor during the second portion of the switching cycle.

An integrated circuit package includes a lead frame and an encapsulation that substantially encloses the lead frame. The lead frame further includes a first conductor comprising a first conductive loop and a second conductor galvanically isolated from the first conductor, proximate to and magnetically coupled to the first conductive loop to provide a communication link between the first and second conductor. The second conductor includes a first conductive portion, a second conductive portion, and a wire coupling together the first conductive portion and the second conductive portion.

An apparatus for conversion between AC and DC voltages includes a rectifier and first and second stages coupled to each other and having a regulator and a switched-capacitor circuit respectively. The first stage receives a first voltage from the rectifier and the second stage provides a second voltage. A controller controls the first and second stages.

A system and method for high speed switching comprises receiving voltage inputs at a bridge rectifier, generating a control signal from a transistor, and driving a gate of a field effect transistor (FET) via the control signal of the transistor, wherein a source of the FET is connected to a negative output of the bridge rectifier and a drain of the FET is connected to a positive output of the bridge rectifier through a load. The system and method further comprises limiting current flowing to the gate of the FET through first and second resistors and first and second diodes connecting the voltage inputs to the gate of the FET and limiting voltage to the gate of the FET below a maximum voltage rating of the FET by a Zener diode connected to the gate of the FET.

A converter for conversion between three-phase AC and a DC signal may include three phase terminals, a first and second DC terminal, conversion circuitry for conversion between three phase voltages of the three-phase AC signal and a first and second intermediate voltage at first and second intermediate nodes, and first and second buck circuits. The buck circuits each have three devices that are actively switchable for connecting switch-node terminals to any one of the three phase terminals. The first buck circuit includes a second switching device connected between the first intermediate node and the first switch-node terminal, and a first filter inductor connected between the first switch-node terminal and the first DC terminal. The second buck circuit has another second switching device connected between the second intermediate node and the second switch-node terminal, and a second filter inductor connected between the second switch-node terminal and the second DC terminal.

An electronic interface device between an electromagnetic energy harvesting stage provided with an inductance and a load stage, the electronic interface device being provided to allow tending the charge seen by the harvesting stage towards an optimal charge and thus being able to extract a maximum of energy from this energy harvesting stage.

A voltage-regulating circuit comprising: a voltage regulator, a switch, a first comparing circuit for comparing the amplitude deviation between the input voltage and the output voltage to a first threshold, a second comparing circuit for comparing the amplitude of the output voltage to a second threshold, and a control circuit for commanding the switch to open or close depending on the comparisons made by the first comparing circuit and by the second comparing circuit. Also disclosed is a regulated power-supply module comprising such a voltage-regulating circuit.

The power supply device includes a first winding, a second winding, a third winding, a fourth winding, a first AC-DC conversion unit, a second AC-DC conversion unit, a first power supply terminal and a second power supply terminal. The first and second windings are disposed on a secondary side of a multi-pulse transformer, and coupled to an input of the first AC-DC conversion unit. The first power supply terminal is coupled to an output of the first AC-DC conversion unit. The third and fourth windings are disposed on the secondary side of the multi-pulse transformer, and coupled to an input of the second AC-DC conversion unit. The second power supply terminal is coupled to an output of the second AC-DC conversion unit. Phases of output voltages of the first winding, the third winding, the second winding and the fourth winding are successively shifted left or successively shifted right for 15°.

A system and method for high speed switching comprises receiving voltage inputs at a bridge rectifier, generating a control signal from a transistor, and driving a gate of a field effect transistor (FET) via the control signal of the transistor, wherein a source of the FET is connected to a negative output of the bridge rectifier and a drain of the FET is connected to a positive output of the bridge rectifier through a load. The system and method further comprises limiting current flowing to the gate of the FET through first and second resistors and first and second diodes connecting the voltage inputs to the gate of the FET and limiting voltage to the gate of the FET below a maximum voltage rating of the FET by a Zener diode connected to the gate of the FET.