An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N−1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.

An example log power detector includes a gain or attenuation circuit and a detector circuit. The gain or attenuation circuit includes a plurality of gain or attenuation elements arranged in a sequence, each gain or attenuation element configured to generate an output signal that is an amplified or attenuated version of an input signal provided thereto. The detector circuit includes a plurality of detectors, each detector configured to receive the output signal from a different one of the gain or attenuation elements and to generate a signal indicative of a power of the received output signal. At least the last detector is configured to receive a DC offset signal that is different from a DC offset signal received by at least one other detector. Such a log detector may provide effective noise compensation to reduce errors caused by input noise, especially for low-power and/or high-frequency input signals.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

The driver circuit includes DC cut capacitors, an input buffer, input termination resistors connected in series between differential input signal terminals and an ESD protection circuit connected to a connection point of the input terminal resistors. The ESD protection circuit includes diodes.

The apparatus relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long-Term Evolution (LTE). The disclosure relates to an apparatus including an electronic circuit for amplifying a signal. The apparatus includes a transceiver including an amplification circuit, and at least one processor coupled to the transceiver. The amplification circuit includes a first path to generate a first current corresponding to a voltage of an input signal, a second path to generate a second current corresponding to a voltage of the input signal, a separation unit to control each of the first current and the second current, a current mirror to generate a third current corresponding to the first current, and a folding unit to generate an output signal on the basis of the second current and the third current.

An amplifier circuit includes a first cascode transistor and a second cascade transistor, the first cascade transistor being electrically connected between a first transistor and a first load circuit, the second cascode transistor being electrically connected between a second transistor and a second load circuit. The amplifier circuit includes a first shunt transistor and a second shunt transistor, the first shunt transistor being electrically connected between the first transistor and a first emitter-follower circuit, the second shunt transistor being electrically connected between the second transistor and a second emitter-follower circuit. A differential current signal includes a first differential current and a second differential current, the first differential current flowing through the first cascode transistor and the second cascode transistor, and a second differential current flowing through the first shunt transistor and the second shunt transistor.

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.

An attenuator arrangement comprising at least a first attenuation path configured to couple between a signal processing chain, SPC, and a measurement apparatus; said SPC comprising a first and second SPC terminal, said SPC configured to apply one or both of a gain and phase change on a signal passed between the SPC terminals; said measurement apparatus configured to measure one or both of the gain and the phase change applied by SPC by coupling to and receiving signals from said SPC terminals; wherein one of said first SPC terminal and said second SPC terminal is coupled to the measurement apparatus through said first attenuation path; and wherein the at least first attenuation path of the attenuator arrangement is configured to provide, selectively, for attenuation of the signal to the measurement apparatus to make the signal power of the signals from said SPC terminals more equal.

The invention relates to a gain-control stage (100) for generating gain-control signals (V.sub.c+, V.sub.c−) for controlling an external variable-gain amplifying unit (101). The gain-control stage comprises a first (102) and a second differential amplifier unit (112) that receive, at a respective input interface (104,114) a reference voltage signal (V.sub.Ref) and a variable gain-control voltage signal (V.sub.GC). The second differential amplifier unit is configured to provide, via a second output interface (120), a control voltage signal (V.sub.1) to a controllable first current source (106) of the first differential amplifier unit (102). The first differential amplifier unit (102) is configured to provide, via a first output interface (110), the first and the second gain-control signal (V.sub.C+, V.sub.C−) in dependence on the variable gain-control voltage signal (V.sub.GC), the reference voltage signal (V.sub.Ref) and a first biasing current (I.sub.B1) that depends on the control voltage signal.

An apparatus includes a package and a beam former circuit. The package may be configured to be mounted on an antenna array at a center of four antenna elements. Each antenna element may include a dual-pole antenna having a vertical feed and a horizontal feed. The beam former circuit may be (i) disposed in the package, (ii) have a plurality of pairs of ports, (iii) configured to generate a plurality of radio-frequency signals in the ports while in a transmit mode and (iv) configured to receive the radio-frequency signals at the ports while in a receive mode. Each pair of the ports is configured to be directly connected to a respective one of the antenna elements. All of the ports may be spatially routed into alignment with the vertical feeds and the horizontal feeds in a single conductive plane of the antenna array.