A power amplifier circuit includes a first amplifier that amplifies an input signal and outputs an output signal; a second amplifier that, in accordance with a control signal, amplifies a signal corresponding to the input signal, generates a signal having an opposite phase to that of the output signal, and adds the signal to the output signal; and a control circuit that supplies the control signal to the second amplifier. The control circuit outputs the control signal so that during operation of the power amplifier circuit in a first power mode, a gain of the second amplifier is not less than zero and less than a predetermined level and during operation in a second power mode lower than the first power mode in output power level, a gain of the second amplifier is not less than the predetermined level and less than a gain of the first amplifier.

An amplifier includes a first input transistor, a second input transistor, a first cascode transistor, a second cascode transistor, a first current mirror circuit, and a second current mirror circuit. The first input transistor is coupled to a first input terminal. The second input transistor is coupled to a second input terminal and the first input transistor. The first cascode transistor is coupled to the first input transistor. The second cascode transistor is coupled to the second input transistor and the first cascode transistor. The first current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the first input terminal. The second current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the second input terminal.

A power efficient (PE) amplifier includes a cascode amplifier, a transistor amplifier, and a voltage supply. The transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The voltage supply is low voltage and supplies a current to the cascode amplifier. The PE amplifier further includes a plurality of current sources which provide a total current to the transistor amplifier. The PE amplifier has, among other things, improved power gain, improved reverse isolation, improved power dissipation, and improved peak differential swing.

Differential clamp circuits configured to recirculate the current in one clamp, either low-side clamp or high-side clamp, from one output of a differential signal to the other output of the differential signal are disclosed. Differential clamp circuits described herein may be particularly suitable for providing programmable clamps at differential outputs of an ADC driver and may be particularly beneficial to implement clamps that are symmetrical around an ADC's input common-mode voltage. Some differential clamp circuit described herein may advantageously present a smaller capacitive load at each output, thus reducing bandwidth degradation of the output stage. Furthermore, differential clamp circuits described herein may operate with only one control voltage, making it easier to limit the output excursions symmetrically around the default common-mode voltage.

There is provided a printer including a motor configured to convey a medium and a processor configured to control the motor. The processor acquires a signal corresponding to a counterelectromotive force of the motor and performs predetermined processing based on the acquired signal.

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.

Differential clamp circuits configured to recirculate the current in one clamp, either low-side clamp or high-side clamp, from one output of a differential signal to the other output of the differential signal are disclosed. Differential clamp circuits described herein may be particularly suitable for providing programmable clamps at differential outputs of an ADC driver and may be particularly beneficial to implement clamps that are symmetrical around an ADC's input common-mode voltage. Some differential clamp circuit described herein may advantageously present a smaller capacitive load at each output, thus reducing bandwidth degradation of the output stage. Furthermore, differential clamp circuits described herein may operate with only one control voltage, making it easier to limit the output excursions symmetrically around the default common-mode voltage.

An amplifier includes a first input transistor, a second input transistor, a first cascode transistor, a second cascode transistor, a first current mirror circuit, and a second current mirror circuit. The first input transistor is coupled to a first input terminal. The second input transistor is coupled to a second input terminal and the first input transistor. The first cascode transistor is coupled to the first input transistor. The second cascode transistor is coupled to the second input transistor and the first cascode transistor. The first current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the first input terminal. The second current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the second input terminal.

A power efficient (PE) amplifier includes a cascode amplifier, a transistor amplifier, and a voltage supply. The transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The voltage supply is low voltage and supplies a current to the cascode amplifier. The PE amplifier further includes a plurality of current sources which provide a total current to the transistor amplifier. The PE amplifier has, among other things, improved power gain, improved reverse isolation, improved power dissipation, and improved peak differential swing.

A programmable gain amplifier includes a first gain stage having a first bias current path and a first intermediate node, a second gain stage having a second bias current path and a second intermediate node, a third gain stage having a third bias current path and a third intermediate node, a fourth gain stage having a fourth bias current path and fourth intermediate node, a first resistor coupled between the first intermediate node and the second intermediate node, and a second resistor coupled between the third intermediate node and the fourth intermediate node.