An apparatus include a package, a chip and a plurality of bumps. The package may include (i) a plurality of bonding pads configured to exchange a plurality of radio-frequency signals with an antenna panel and (ii) a plurality of transmission lines configured to exchange the radio-frequency signals with the bonding pads. Two of the transmission lines may be connected to each of the bonding pads. The chip may be disposed in the package and may include (i) a plurality of transceiver channels configured to exchange the radio-frequency signals with the transmission lines and (ii) a plurality of switches configured to switch the radio-frequency signals to a signal ground. The bumps may be configured to exchange the radio-frequency signals between the transmission lines of the package and the transceiver channels of the chip. The transmission lines, the bumps and the switches may form a plurality of transmit/receive switches.

A radio-frequency device comprises a first radio-frequency signal node, a second radio-frequency signal node, a first power cell path coupled between the first radio-frequency signal node and a ground reference node, the first power cell path including a first transistor having an input terminal coupled to the second radio-frequency signal node, and a second power cell path coupled in parallel with the first power cell path between the first radio-frequency signal node and the ground reference node, the second power cell path including a second transistor having an input terminal coupled to the second radio-frequency signal node and an output terminal that is electrically isolated from an output terminal of the first transistor.

An apparatus includes an impedance matching network, a first switch circuit, and a second switch circuit. The impedance matching network generally comprises a first port, a second port, and a third port. The first switch circuit may be coupled between the first port and a circuit ground potential. The second switch circuit may be coupled between the second port and the circuit ground potential. The impedance matching network generally provides a first impedance value for the first port and for the third port when the second port is connected to the circuit ground potential. The impedance matching network generally provides a second impedance value for the second port and for the third port when the first port is connected to the circuit ground potential. The first impedance value and the second impedance value are asymmetrical.

A power amplifier circuit for broadband data communication over a path in a communication network can reduce or avoid gain compression, provide low distortion amplification performance, and can accommodate a wider input signal amplitude range. A dynamic variable bias current circuit can be coupled to a common emitter bias node of a differential pair of transistors to provide a dynamic variable bias current thereto as a function of an input signal amplitude of an input signal. Bias current is increased when input signal amplitude exceeds a threshold voltage established by an offset or level-shifting circuit. The frequency response of the bias current circuit can track the frequency content of the input signal. A delay in the signal path to the differential pair can phase-align the bias current to the amplification by the differential pair. A dynamic variable supply voltage can be based on an envelope of the input signal.

In an exemplary embodiment, a plurality of differential amplification circuits has: first differential amplification circuits each including a differential pair circuit to generate the differential signal according to the differential input signal, a delay line, and a current source to supply a current to the differential pair circuit via the delay line; and second differential amplification circuits each including a differential pair circuit to generate the differential signal according to the differential input signal, and a current source to directly supply a current to the differential pair circuit. The first differential amplification circuits and the second differential amplification circuits are mutually connected in parallel between the pair of input-side transmission lines and the pair of output-side transmission lines.

An input stage of an operational amplifier receives first and second input voltages. An output slew detection circuit decreases a first current responsive to slewing of an output of the operational amplifier and increases the first current responsive to no slewing. A slew boost and differential input voltage detection generates a second current at a first level when the first and second input voltages are approximately equal and to generate the second current at a second level, smaller than the first level, responsive to the first and second input voltages not being approximately equal. A voltage on a capacitor increases responsive to the first current from the output slew detection circuit increasing and responsive to the second current being at the second level. A current mirror is activated responsive to the voltage on the capacitor exceeding a second threshold. The current mirror decreases a third current of the input stage.

An operational amplifier includes an input stage configured to receive a first input voltage and a second input voltage and a slew boost circuit coupled to the input stage and configured to selectively increase current through the input stage. The operational amplifier also includes an output stage coupled to the input stage and configured to generate an output voltage, and a slew boost disable circuit configured to assert a control signal to the slew boost circuit to disable the slew boost circuit. The slew boost circuit is disabled when both: the first input voltage being more than a first threshold voltage different from the second input voltage and the output voltage failing to change by more than a second threshold rate.

An input stage of an operational amplifier receives first and second input voltages. An output slew detection circuit decreases a first current responsive to slewing of an output of the operational amplifier and increases the first current responsive to no slewing. A slew boost and differential input voltage detection generates a second current at a first level when the first and second input voltages are approximately equal and to generate the second current at a second level, smaller than the first level, responsive to the first and second input voltages not being approximately equal. A voltage on a capacitor increases responsive to the first current from the output slew detection circuit increasing and responsive to the second current being at the second level. A current mirror is activated responsive to the voltage on the capacitor exceeding a second threshold. The current mirror decreases a third current of the input stage.

A cascode power cell for a power amplifier circuit includes a radio frequency signal input node, a radio frequency signal output node, and a plurality of sub-cells each including a first transistor having a collector coupled to the radio frequency signal output node, each of the plurality of sub-cells further including a second transistor having a collector coupled to an emitter of the first transistor at a connection node, and a base coupled to the radio frequency signal input node, the connection nodes for each of the plurality of sub-cells being electrically isolated from one another.

An integrated amplifier device includes a main amplifier configured to be coupled to an input source. A replica amplifier is coupled to the main amplifier to provide a bias to the main amplifier. A transconductance biasing cell to the main amplifier and the replica amplifier. The transconductance biasing cell is configured to bias both the main amplifier and the replica amplifier. A method of making an integrated amplifier device is also disclosed.