A low-noise amplifier includes a low-noise amplifier stage and a filtering and biasing stage. The low-noise amplifier stage receives an input signal and provides a first output signal in response thereto. The low-noise amplifier stage includes a gain element for proving the first output signal, and at least one lowpass filter circuit in series between a first power supply voltage terminal and the gain element having a conductivity determined by lowpass filtering a signal at a bias terminal, and a filtering and biasing stage having an input for receiving the first output signal, and an output for providing a second output signal, and at least one cascode element having a first current conduction path coupled in series between the bias terminal and the output, and having a predetermined filter characteristic.

An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain- stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

A variable gain amplifier includes a first transistor group which is connected to an input terminal and an output terminal, and which amplifies a signal from the input terminal to output the amplified signal to the output terminal; a second transistor group connected to the input terminal; a third transistor group connected to the output terminal; and a controller configured to control the first transistor group, the second transistor group, and the third transistor group so that a total number of the number of transistors to be turned on in the first transistor group and the second transistor group is kept at a constant value, and total numbers of transistors to be turned on in the first transistor group and in the third transistor group are the same.

A fully-differential two-stage operational amplifier circuit is provided, and it includes a first-stage amplification circuit, a second-stage amplification circuit, a common-mode signal acquisition circuit, a common-mode feedback circuit and a bias circuit. The first-stage amplification circuit has a telescopic structure and receives differential input signals IN.sub.P and IN.sub.N. The second-stage amplification circuit has a common-source structure and outputs differential output signals OUT.sub.P and OUT.sub.N. The common-mode signal acquisition circuit receives differential output signals, and outputs an operational amplifier output common-mode signal V.sub.CMO. The common-mode feedback circuit outputs common-mode feedback signals VB.sub.1 and VB.sub.2 to the first-stage amplifier circuit and the second-stage amplifier circuit respectively; The bias circuit outputs a bias voltage VB.sub.3 to the first-stage amplifier circuit, and outputs bias voltages VB.sub.4 and VB.sub.5 to the first-stage amplifier circuit respectively.

A transimpedance amplifier circuit includes an amplifier circuit that converts a current signal into a voltage signal with a gain being varied based on a control signal and a gain control circuit that generates the control signal based on an amplitude of the voltage signal. The gain control circuit includes a detection circuit that generates an amplitude-detection-signal in accordance with the amplitude of the voltage signal, a setting circuit that generates an amplitude-reference-signal, a differential voltage generation circuit that generates a differential-voltage-signal obtained by offsetting a voltage difference between the amplitude-detection-signal and the amplitude-reference-signal based on an amplitude-setting-signal, an operational transconductance amplifier (OTA) that generates a differential-current-signal based on the differential-voltage-signal, and a variable capacitor circuit having a variable capacitance being varied based on the amplitude-setting-signal, and configured to be charged/discharged by the differential-current-signal and output a charging voltage. The control signal is generated based on the charging voltage.

An apparatus is disclosed for controlling a power amplifier that is coupled to an antenna element of an antenna array. In example implementations, an apparatus includes an antenna element of an antenna array and a power amplification system. The power amplification system includes at least one input node, at least one output node coupled to the antenna element, and at least one power amplifier branch coupled between the at least one input node and the at least one output node. The power amplification system also includes at least one feedback node coupled to the at least one output node, at least one control node, and a feedback control loop coupled between the at least one feedback node and the at least one control node.

A device for analysis of cells comprises: an active sensor area (104) presenting a surface for cell growth; a microelectrode array (102) comprising a plurality of pixels (110) in the active sensor area (104), wherein each pixel (110) comprises at least one electrode (120) at the surface, wherein each pixel (110) is configured to control the configuration of the pixel circuitry and set a measurement modality of the pixel; recording circuitry having a plurality of recording channels (130), wherein each pixel (110) is connected to a recording channel (130), wherein each recording channel (130) comprises a reconfigurable component (131), which is selectively controlled between being set to a first mode, in which the reconfigurable component (131) is configured to amplify a received pixel signal, and being set to a second mode, in which the reconfigurable component (131) is configured to selectively pass a frequency band of the received pixel signal.

An amplifier circuit includes an input circuit configured to receive the first and second input signals and control signal levels of first and second nodes, an output circuit configured to generate signal levels of first and second output signals based on the signal level of the first node and the signal level of the second node, a charge circuit configured to precharge the first and second nodes or discharge the first and second nodes based on a logic level of a control signal, and a reset circuit configured to maintain the signal levels of the first and second output signals at previously determined signal levels based on the logic level of the control signal.

An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more power amplifiers for amplifying a signal for transmission through the antenna. A power amplifier may include a phase distortion compensation circuit. The phase distortion compensation circuit may include one or more n-type metal-oxide-semiconductor capacitors configured to receive a bias voltage. The bias voltage may be set to provide the proper amount of phase distortion compensation.

Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. A receiver may use a modulation scheme to communicate information with a host device. The receiver may include a first circuit, a second circuit, a third circuit, and a fourth circuit. Each of the first circuit, the second circuit, the third circuit, and the fourth circuit may determine, for a respective clock phase, a voltage level of a signal modulated using the modulation scheme. The receiver may include a first feedback circuit, a second feedback circuit, a third feedback circuit, and a fourth feedback circuit. The first feedback circuit that may use information received from the first circuit at the first clock phase and modify the signal input into the second circuit for the second clock phase.