Patent classifications
H03F3/45192
Methods and apparatus for an amplifier integrated circuit
Various embodiments of the present technology may provide methods and apparatus for an amplifier integrated circuit. The amplifier integrated circuit may provide two amplifiers, one amplifier set to a low gain bandwidth product to amplify at a higher speed and the other amplifier set to a high gain bandwidth product to amplify at a lower speed. The amplifier integrated circuit may further provide a switching circuit connected to the amplifiers, wherein the switching circuit is responsive to a control signal and operates to selectively activate the high speed amplifier and the low speed amplifier in sequence.
Operational amplifier circuit and display apparatus with operational amplifier circuit for avoiding voltage overshoot
An operational amplifier circuit in a display apparatus which is fast-acting to prevent voltage overshoot comprises a pre-operational amplifier module, an output operational amplifier module, and an output module. Driving current from the pre-operational amplifier module is the basis of the output operational amplifier module generating a dynamic bias voltage to the output module. The output operational amplifier module detects the dynamic bias voltage and adjusts the bias voltage to be level with a specified voltage based on at least one control voltage. When the dynamic bias voltage is less than the specified voltage, the output operational amplifier module pulls up the bias voltage and when the bias voltage is larger than the specified voltage, the output operational amplifier module pulls down the bias voltage. The pull up and pull down speeds are proportional to the at least one control voltage.
Precision high frequency phase adders
An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.
OPERATIONAL AMPLIFIER OFFSET TRIM
An integrated circuit (IC) includes first, second, third, and fourth transistors, first and second current source devices, and a trim circuit. The first transistor has a first control input and a first current terminal. The second transistor has a second control input and a second current terminal. The third transistor had a third control input and third and fourth current terminals. The fourth transistor has a fourth control input and fifth and sixth current terminals. The first current source is coupled between a first power supply node and the third current terminal. The second current source is coupled between the first supply node and the fifth current terminal. The trim circuit is coupled between the fourth current terminal and a second power supply node, and is coupled between the sixth current terminal and the second power supply node. The trim circuit includes a resistive digital-to-analog converter (RDAC) circuit.
Transmission device and transmission/reception system
A transmission/reception system 1 includes a transmission device 10 and a reception device 20 that is connected to each other through differential signal lines 30 and a signal line 40, and receives a differential signal that is sent out from the transmission device 10 using the reception device 20. The transmission device 10 includes a signal output unit 11, a request input unit 12, and a resistor 13. The signal output unit 11 sends out a differential signal from a pair of output terminals P.sub.111 and P.sub.112 that are connected to the differential signal lines 30. A common voltage of each of the pair of output terminals P.sub.111 and P.sub.112 is constant over a state where no electric power is supplied and an idle state.
OPERATIONAL AMPLIFIER USING SINGLE-STAGE AMPLIFIER WITH SLEW-RATE ENHANCEMENT AND ASSOCIATED METHOD
An operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier receives an input signal, and amplifies the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller receives the input signal, and generates the bias voltage input according to the input signal.
Low noise amplifier circuit for a thermal varying resistance
A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.
AMPLIFER BIASING TECHNIQUES
Techniques for biasing output transistor of a push-pull amplifier output stage are provided. In certain applications the techniques can improve efficiency of the amplifier. In an example, a circuit can include an output stage including first and second output transistors, a first scaled replica transistor corresponding to the first output transistor, and an amplifier circuit in a feedback arrangement for biasing a gate of the first output transistor at a level that, at a specified stand-by current level of the first output transistor, reproduces a voltage difference between the drain and source terminals of the first output transistor across the drain and source terminals of the first replica transistor.
OPERATIONAL AMPLIFIER CIRCUIT AND DISPLAY APPARATUS WITH OPERATIONAL AMPLIFIER CIRCUIT FOR AVOIDING VOLTAGE OVERSHOOT
An operational amplifier circuit in a display apparatus which is fast-acting to prevent voltage overshoot comprises a pre-operational amplifier module, an output operational amplifier module, and an output module. Driving current from the pre-operational amplifier module is the basis of the output operational amplifier module generating a dynamic bias voltage to the output module. The output operational amplifier module detects the dynamic bias voltage and adjusts the bias voltage to be level with a specified voltage based on at least one control voltage. When the dynamic bias voltage is less than the specified voltage, the output operational amplifier module pulls up the bias voltage and when the bias voltage is larger than the specified voltage, the output operational amplifier module pulls down the bias voltage. The pull up and pull down speeds are proportional to the at least one control voltage.
AUTO-ZERO APPLIED BUFFER FOR DISPLAY CIRCUITRY
A system includes a pixel that emits light based on a signal provided to the pixel. The system may also include a buffer circuit having a differential pair stage, a cascade stage, and an output stage. The differential pair stage may receive a common mode voltage signal via a first switch in response to the first switch receiving a first signal that causes the first switch to close. The differential pair stage may couple a capacitor to the output stage via a second switch that operate based on a second signal, such that the capacitor reduces an offset provided by one or more circuit components in the differential pair stage, the cascade stage, the output stage, or any combination thereof. The differential pair stage may output the common mode voltage to the pixel via the output stage in response to the first signal being present.