An amplifier includes an input stage. The input stage includes a differential pair and a load circuit. The differential pair includes a first transistor and a second transistor. The first transistor and the second transistor are configured to amplify a received differential signal. The load circuit connects the differential pair to a reference voltage. The load circuit is configured to vary in resistance in inverse proportion to the transconductance of the first transistor and the second transistor.

In a Class-D amplifier, first/second ratios and first/second RC time constants are sequentially matched by trimming. An integrator is coupled to differential first/second paths. The first/second ratios are of a feedback resistor to an input resistor in the first/second paths. R's of the first/second RC time constants are the resistors of the first/second matched ratios. C's of the first/second RC time constants are integrating capacitors in the first/second path. For each of multiple power rails, a ramp amplitude is determined based on a sensed voltage. Concurrently, the driver stage is switched from first to second power rails and quantizer switched from first to second ramp amplitudes to achieve constant combined quantizer/driver stage gain. Based on a sensed load current, an IR drop is determined for a respective output impedance of the driver stage and added to a loop filter output to compensate for the respective output impedance.

An amplifier circuit includes: an amplifier; and a bias circuit that controls an operation point of the amplifier. The amplifier includes: a load resistor; a differential transistor pair electrically coupled to the load resistor; and a tail transistor electrically coupled to the differential transistor pair. The bias circuit includes: a voltage generator circuit that generates a reference voltage corresponding to a sum of a threshold voltage of a transistor in the differential transistor pair and a saturation drain voltage of the tail transistor; and a current generator circuit that generates a reference current that is proportional to a difference between a power supply voltage of the amplifier circuit and the reference voltage by using a reference resistor. The current generator circuit is electrically coupled to the amplifier such that a tail current that flows through the tail transistor is proportional to the reference current.

A sensing system with an AC feedback to the non-signal and non-biased terminal of the transducer. An impedance element, such as two anti-parallel diodes, are provided at the amplifier input, and the amplifier gain is negative and has a size sufficient to ensure that the input on the one terminal does not exceed the forward voltage of the diode.

Amplifier configuration for load-line enhancement is described herein. In some implementations, an apparatus includes an amplifier. The amplifier includes at least one plus transistor stack, at least one minus transistor stack, and at least one inductor. The at least one plus transistor stack is coupled to a plus amplifier node and a plus input node. The at least one minus transistor stack is coupled to a minus amplifier node and a minus input node. The at least one inductor is coupled between the plus amplifier node and the minus amplifier node, with the at least one inductor including an inter-inductor node. The amplifier also includes a minus power switch coupled between the minus amplifier node and one or more supply voltages and an inductor power switch coupled between the inter-inductor node and at least one supply voltage.

A semiconductor device includes a differential amplification circuit that outputs differential output signals Vo1 and Vo2, external output terminals PD1 and PD2 to which one of the differential output signals Vo1 and Vo2 and single end signals Vo3 and Vo4 is selectively supplied, switch units SW1 and SW2 that control a conduction state between the external output terminal PD1 and the feedback line and a conduction state between the external output terminal PD2 and the feedback line, respectively, resistance elements R1 and R2 respectively provided in series with the switch units SW1 and SW2, a CMFB circuit that controls a common mode voltage of the differential amplification circuit according to a difference between an intermediate voltage Vcm of the external output terminals PD1 and PD2 in the feedback line and a reference voltage Vref, and a switch unit SW3 that controls to supply a clamp voltage to the feedback line.

A signal transceiver includes a signal transmitter driving a first differential link between a supply voltage of the signal transmitter and a fraction of the supply voltage, and driving a second differential link between the faction of the supply voltage and a reference ground. The signal transceiver also includes a signal receiver in which the first differential link is coupled to a gate node of an NMOS transistor and to a source node of a PMOS transistor; and the second differential link is coupled to a source node of the NMOS transistor and to a gate node of the PMOS transistor.

An apparatus may include a delta sigma modulator. A first portion of the delta sigma modulator may form a digital predictor while a second portion of the delta sigma modulator may form an analog approximator. An output of the analog approximator may be coupled with a quantizer. The digital predictor, the analog approximator, and the quantizer may form a digitizing loop configured to convert an analog input into a digital output. The digital predictor may be configured to generate, based on a polarity of one or more digital outputs from the quantizer, a digital prediction of an expected amplitude of the analog input. The quantizer may be configured to respond to the digital prediction by adjusting a dynamic range of the digitizing loop including by changing a quantization step size used by the quantizer to quantize the analog input. Related methods are also provided.

A class AB amplifier with improved DC gain. An amplifier includes an input stage and an output stage. The output stage is configured to amplify an output of the input stage. The output stage includes output transistors, class AB amplifier circuitry, minimum selector circuitry, and gain boost amplifier circuitry. The class AB amplifier circuitry includes a first transistor and a second transistor connected as a differential amplifier. The minimum selector circuitry is configured to control bias current in the output transistors by driving a control input of the first transistor. The gain boost amplifier circuitry is coupled to the class AB amplifier circuitry. The gain boost amplifier circuitry is configured to drive a common mode signal onto the control input of the first transistor and a control input of the second transistor, the common mode signal based on the output of the input stage.

The present disclosure provides a differential input circuit. The differential input circuit includes: a P-channel FET differential input pair; an N-channel FET differential input pair; a first power line configured to receive a first voltage; a second power line configured to receive a second voltage lower than the first voltage; a first P-channel FET; a constant current source (CS1) disposed between the first power supply line and the P-channel FET differential input pair as well as the first P-channel FET; a current mirror circuit disposed between the first P-channel FET as well as the N-channel FET differential input pair and the second power supply line; and a logic circuit configured to supply a binarized logic signal to a gate of the first P-channel FET.