Patent classifications
H03F3/45748
METHODS AND APPARATUS FOR DRIVER CALIBRATION
Various embodiments of the present technology may comprise methods and apparatus for driver calibration. The methods and apparatus may comprise various circuits and/or systems to minimize an offset output current (e.g., a drive current) due to an offset voltage in an operational amplifier. The methods and apparatus may comprise a current comparator circuit and a replica circuit that operate in conjunction with each other to monitor the drive current and provide a feedback signal, which is then used to adjust the drive current and improve the accuracy of the drive current.
Variable gain amplifier, correction method and receiving device
To provide a variable gain amplifier capable of correcting a DC offset voltage through simpler control even when a gain thereof is changed. A differential output type variable gain amplifier is equipped with a first voltage correction unit coupled to a preceding stage of a variable gain amplifier circuit and for outputting a first correction voltage to correct a potential difference generated between a first conductor provided with a first input resistor and a second conductor provided with a second input resistor, and a second voltage correction unit coupled to a subsequent stage of the variable gain amplifier circuit and for correcting a differential output. A control unit is configured to control the first correction voltage and a correction amount of a potential difference by the second voltage correction unit and thereby attenuate a DC offset voltage included in the differential output.
Methods and apparatus for driver calibration
Driver circuits, systems for driving actuators, and imaging systems with actuators. The driver circuit includes a current comparator circuit, a driver, and a replica circuit. The current comparator circuit includes a first node having a first voltage. The current comparator circuit also includes a second node having a second voltage. The driver includes a first terminal responsive to the second voltage. The driver also includes a second terminal connected to a reference voltage. The replica circuit includes a third terminal connected to the first node. The replica circuit also includes a fourth terminal connected to the second terminal of the driver. The replica circuit also includes a fifth terminal connected to the first terminal of the driver.
TWO-STAGE COMMON-MODE FEEDBACK CIRCUIT AND FULLY DIFFERENTIAL OPERATIONAL AMPLIFIER INCLUDING THE SAME
A two-stage common-mode feedback (CMFB) circuit and a fully differential operational amplifier are provided. The two-stage CMFB circuit includes a first CMFB circuit and a second CMFB circuit. The first CMFB circuit includes a first CMFB component that receives a first differential pair of output signals of the first amplifier and a first reference signal. The first CMFB component generates a first control signal to regulate a first common-mode voltage of the first amplifier to a first reference voltage of the first reference signal. The second CMFB circuit includes a second CMFB component that receives a second differential pair of output signals of the second amplifier and a second reference signal. The second CMFB component generates a second control signal according to a second reference signal, so as to regulate a second common-mode voltage of the second amplifier to a second reference voltage of the second reference signal.
Amplifier and semiconductor apparatus using the same
An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal.
Offset Cancellation Scheme
An offset cancellation circuit and method are provided where successive stages of cascaded amplifiers are operated in a saturated state. Biasing is provided, by a feedback amplifier, connected in a feedback loop for each cascaded amplifier, so as to be responsive, in a non-saturated state, to the input of an associated amplifier stage operating in the saturated state.
Transconductance amplifier of high linearity and common-mode rejection
A transconductance amplifier includes a first MOS transistor configured to receive a first voltage at a first node and output a first current to a fifth node in accordance with a third voltage at a third node; a second MOS transistor configured to receive a second voltage at a second node and output a second current to a sixth node in accordance with a fourth voltage at a fourth node; a third MOS transistor configured to output a third current to the third node in accordance with a fifth voltage at the fifth node; a fourth MOS transistor configured to output a fourth current to the fourth node in accordance with a sixth voltage at the sixth node; and a source degeneration network placed across the third node and the fourth node.
Peak detector and operational amplifier circuit therein
A peak detector utilizes two choppers to cancel offset voltage of a transconductance amplifier, so the influence of the offset voltage is preventable and the peak detection accuracy of the peak detector can be improved significantly.
HIGH GAIN, LOW-OFFSET, CLASS AB AMPLIFIER CIRCUIT
An amplifier circuit including a first folded double cascode stage configured to receive a differential input signal at a first pair of input transistors and generate a first drive signal, a second folded double cascode stage configured to receive the differential input signal at a second pair of input transistors and generate a second drive signal, and an output stage. The output stage includes a PMOS common-source output transistor configured to receive the first drive signal at its gate, and an NMOS common-source output transistor configured to receive the first drive signal at its gate, the PMOS common-source output transistor and NMOS common-source output transistor being jointly configured to generate an output signal based on the first drive signal and the second drive signal.
AMPLIFIER AND SEMICONDUCTOR APPARATUS USING THE SAME
An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal.