During operation of an analog filter having one or more filter stages is configured to operate in a first configuration. Configuring the analog filter to operate in the first filter configuration includes configuring one or both of i) a filter response of the analog filter and ii) a filter bandwidth of the analog filter. A first set of one or more direct current (DC) offset correction codes corresponding to the first filter configuration are retrieved from a memory. The one or more DC offset correction codes in the first set are converted to one or more first analog DC offset correction signals. While operating the analog filter configured in the first configuration, the one or more first analog DC offset correction signals are applied to the one or more filter stages of the analog filter.

An operational amplifier is disclosed. The operational amplifier activates/couples either a first or a second differential pair of transistors to an input based on the input voltage. The first and second pair of transistors are each biased with a current having a first portion that is constant with temperature and a second portion that is proportional to temperature. By adjusting the ratios of the first and second portions, the transconductance of each differential pair may be made relatively constant with temperature. Each differential pair is coupled to a trim current source that is adjusted to reduce the voltage offset at each output. The resulting voltage offset for the operational amplifier is relatively constant over a range of input voltages and has temperature coefficient unaffected by the trimming process.

Methods and systems are described for generating a time-varying information signal at an output of a variable gain amplifier (VGA), sampling, using a sampler having a vertical decision threshold associated with a target signal amplitude, the time-varying information signal asynchronously to generate a sequence of decisions from varying sampling instants in sequential signaling intervals, the sequence of decisions comprising (i) positive decisions indicating the time-varying information signal is above the target signal amplitude and (ii) negative decisions indicating the time-varying information signal is below the target signal amplitude, accumulating a ratio of positive decisions to negative decisions, and generating a gain feedback control signal to adjust a gain setting of the VGA responsive to a mismatch of the accumulated ratio with respect to a target ratio.

A current sensing amplifier circuit includes: an amplifier configured to generate an output voltage correlated with a current to-be-sensed according to a first input voltage at a first input end and a second input voltage at a second input end in a normal operation mode; and a current source circuit configured to generate a trimming current according to the first input voltage and a reference voltage in a trimming mode and to provide the trimming current to trim an offset referred to input (RTI) voltage generated by the current sensing amplifier circuit in the normal operation mode. The current source circuit is coupled between: a first resistor and a non-inverting input end, a second resistor and the output voltage, a third resistor and the non-inverting input end, or a fourth resistor and an inverting input end.

A comparator offset voltage self-correction circuit is disclosed. A comparator offset voltage which is caused by the semiconductor process parameter randomness also has randomness. Due to the randomness of the comparator offset voltage, a reference voltage of a parallel comparator in a parallel-conversion-type analog-to-digital converter is uncertain. If the comparator offset voltage is large, the parallel-conversion-type analog-to-digital converter may even have a functional error. The comparator offset voltage self-correction circuit provided in the present invention can correct a random offset voltage of a comparator to meet requirements. Therefore, by means of the circuit and a method provided in the present invention, adverse influence of the random offset of the comparator on the function and the performance of the parallel-conversion-type analog-to-digital converter is eliminated, thereby greatly improving the speed and the performance of the analog-to-digital converter, in particular the parallel-conversion-type analog-to-digital converter.

An amplifier circuit includes: an input circuit configured to receive an input signal; a load circuit provided in series with the input circuit and including a first variable resistance unit and a second variable resistance unit, a resistance value of the first variable resistance unit being controlled by, a digital code, a resistance value of the second variable resistance unit being controlled by an analog control voltage; and a correction circuit including a third variable resistance unit having a circuit configuration corresponding to the first variable resistance unit and a fourth variable resistance unit having a circuit configuration corresponding to the second resistance unit, a resistance value of the third variable resistance unit being controlled by the digital code, a resistance value of the fourth variable resistance unit being controlled by the analog control voltage, the correction circuit being configured correct a resistance value of the load circuit.

Disclosed are an operational amplifier and a method for reducing an offset voltage of the operational amplifier, which control an auxiliary circuit to generate a first auxiliary current and a second auxiliary current by adjusting the resistance of a resistance regulator, thereby adjusting a first current and a second current outputted from an input-stage circuit and further adjusting the offset voltage of the operational amplifier. Therefore, the operational amplifier and the method for reducing the offset voltage of the operational amplifier use the resistors to adjust the offset voltage so as to reduce the Least Significant Bit (LSB) distribution, thereby enhancing the accuracy of the offset voltage.

Disclosed are an operational amplifier and a method for reducing an offset voltage of the operational amplifier, which control an auxiliary circuit to generate a first auxiliary current and a second auxiliary current by adjusting the resistance of a resistance regulator, thereby adjusting a first current and a second current outputted from an input-stage circuit and further adjusting the offset voltage of the operational amplifier. Therefore, the operational amplifier and the method for reducing the offset voltage of the operational amplifier use the resistors to adjust the offset voltage so as to reduce the Least Significant Bit (LSB) distribution, thereby enhancing the accuracy of the offset voltage.

A semiconductor device includes an operational transconductance amplifier (OTA) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the OTA. Measurement circuitry is coupled to measure offset in the OTA. Control logic is configured to operate the first and second sets of switches to couple input transistors of a first group of the configuration units to the first transistor of the matched pair of transistors, and to couple input transistors of a remaining group of the configuration units to the second transistor of the matched pair of transistors. Settings of the first and second sets of switches are selected to minimize the offset.

A semiconductor device includes an operational transconductance amplifier (OTA) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the OTA. Measurement circuitry is coupled to measure offset in the OTA. Control logic is configured to operate the first and second sets of switches to couple input transistors of a first group of the configuration units to the first transistor of the matched pair of transistors, and to couple input transistors of a remaining group of the configuration units to the second transistor of the matched pair of transistors. Settings of the first and second sets of switches are selected to minimize the offset.