A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

A latch circuit having a master latch and a slave latch includes a device used to short either the master latch or the slave latch. The device includes a transistor and a global control used to assert a signal, and is positioned to short an inverter of the master latch or the slave latch. When the signal is asserted by the global control, the inverter is shorted such that the output value of the inverter is the same as the input value. The assertion of the signal is facilitated by another device connected to the master latch and the slave latch that includes the global control and a transistor.

The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit. The second time delay circuit further includes a second gate-conductor and a second gate via-connector in direct contact with the second gate-conductor. The second gate-conductor intersects a first-type active region structure and a second-type active region structure in a second area, and wherein at least a portion of the second gate via-connector is atop the second-type active region structure

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit. The second time delay circuit further includes a second gate-conductor and a second gate via-connector in direct contact with the second gate-conductor. The second gate-conductor intersects a first-type active region structure and a second-type active region structure in a second area, and wherein at least a portion of the second gate via-connector is atop the second-type active region structure

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

A register circuit includes a first pulse-latch circuit configured to store data from a first input node. A multiplexer circuit is configured to select between an output of the first pulse-latch circuit and a second input node. A second pulse-latch circuit is configured to store data provided by the multiplexer circuit. A control circuit is configured to switch, in response to a configuration signal, the register circuit between a flip-flop mode and a dual-latch mode.

A flip-flop circuit for enhancing clock rates in high speed electronic circuits, the flip-flop circuit having an input terminal, an output terminal, and a third terminal that controls the flow of signal from the input terminal to the output terminal, comprising: two latches arranged in a master-slave configuration such that the input terminal of the first latch is also the input terminal of the flip-flop and the output terminal of the second latch is also the output terminal of the flip-flop; and at least one feedback path that adds signal to the input of the flip-flop from one of the outputs of the two latches.