A flip-flop device is provided. The flip-flop device includes a first flip-flop and a clock controller. The first flip-flop receives a first clock signal and a second clock signal for operation. The clock controller receives a clock source signal and generates the first clock signal and the second clock signal according to the clock source signal. Each of the first clock signal and the second clock signal switches between a first voltage level and a second voltage level. For each of the first clock signal and the second clock signal, a period of the first voltage level is shorter than a period of the second voltage level. The period of the first voltage level of the first clock signal and the period of the first voltage level of the second clock signal are non-overlapping.

A flip-flop circuit including a first logic circuit, a first master latch, a second master latch, and a slave latch is provided. The first logic circuit operates a logic operation on a selecting signal and a clock signal to generate a first control signal. The first master latch receives a data signal according to the first control signal and latches the data signal according to the selecting signal and the clock signal. The second master latch receives a scan data signal according to the selecting signal and the clock signal, wherein an output terminal of the second master latch is directly connected to an output terminal of the first master latch. The slave latch latches a signal on the output terminals of the first and second master latches for generating an output signal.

Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.

A 24-transistor D flip-flop circuit operates in a sampling mode when a clock signal has a first voltage state, and a holding mode when the clock signal has a second voltage state. The flip-flop circuit includes an internal control node coupled to a reference voltage node by way of a transistor controllable to couple the internal control node to the reference voltage node when the clock signal has the second voltage state. The flip-flop has very low power dissipation as it includes a 4-transistor change-sense component to detect changes in input data. The change-sense component is coupled in series with the transistor and receives an indication of an input voltage state of the flip-flop circuit and an indication of an output voltage state of the flip-flop circuit, and inhibits toggling of the internal control node if the indicated input voltage state and the indicated output voltage state are the same.

A latch circuit having a master latch and a slave latch includes a device used to short either the master latch or the slave latch. The device includes a transistor and a global control used to assert a signal, and is positioned to short an inverter of the master latch or the slave latch. When the signal is asserted by the global control, the inverter is shorted such that the output value of the inverter is the same as the input value. The assertion of the signal is facilitated by another device connected to the master latch and the slave latch that includes the global control and a transistor.

A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IC, and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.

In one or more embodiments, an integrated circuit includes a programmable memory, a key generation module and a module. The programmable memory is to maintain a first key portion. The key generation module is to generate a key using the first key portion from the programmable memory and a second key portion received via a memory interface. The module is to encrypt or decrypt data using the key.

In one or more embodiments, an integrated circuit includes a programmable memory, a key generation module and a module. The programmable memory is to maintain a first key portion. The key generation module is to generate a key using the first key portion from the programmable memory and a second key portion received via a memory interface. The module is to encrypt or decrypt data using the key.

A master slave storage circuit can include a first master portion coupled to a first master data storage node and a first slave portion coupled to a first slave data storage node. The first master portion can comprise one of a first master latch or a first master capacitive element coupled to the first master data storage node and the first slave portion comprises one of a first slave latch or a first slave capacitive element coupled to the first slave data storage node. If the first master portion comprises the first master latch, the first slave portion comprises the first slave capacitive element, and if the first master portion comprises the first master capacitive element, the first slave portion comprises the first slave latch.

Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.