A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C.sup.3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C.sup.3MOS logic with low power conventional CMOS logic. The combined C.sup.3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

In a semiconductor integrated circuit, a first analog circuit block operates by a voltage applied between a first node and a third node. Each of a plurality of first current sources has a first end connected to the third node and a second end connected to the first analog circuit block. The plurality of first current sources function as current sourcing or current sinking for the first analog circuit block. A first switch group is provided between the plurality of first current sources and the first analog circuit block, and in a test mode, individually switches electrical connection of the second end of each of the plurality of first current sources from the first analog circuit block to a second node.

In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C.sup.3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C.sup.3MOS logic with low power conventional CMOS logic. The combined C.sup.3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

A phase detector including a first latch and a control circuit is provided. The first latch generates a first output signal and a second output signal in response to a phase difference between a first input signal and a second input signal. Each of the first and second output signals includes first phase information and second phase information of the phase difference. The control circuit generates a phase indicating signal in response to the first phase information of the phase difference. The phase indicating signal indicates a relative position between the first input signal and the second input signal.