According to certain aspects, a method for clock gating includes receiving an enable signal, and latching a logic value of the enable signal on an edge of an input clock signal. The method also includes passing the latched logic value of the enable signal to a clock-gating output when the input clock signal is logically high, blocking the latched logic value of the enable signal from the clock-gating output when the input clock signal is logically low, and pulling the clock-gating output logically low when the input clock signal is logically low.

The present disclosure relates to a D flip-flop having a multiplexer function, including: a first transmission gate whose data input end is configured to receive a first data signal and whose clock input end is configured to receive a first clock signal; a second transmission gate whose data input end is configured to receive a second data signal and whose clock input end is configured to receive a second clock signal; an inverted latch unit whose data input end is connected to an output end of the first transmission gate and an output end of the second transmission gate and whose clock input end is configured to receive a third clock signal; and an inverter whose input end is connected to an output end of the inverted latch unit and whose output end provides an output of the D flip-flop.

A flip-flop circuit includes a D flip-flop and a gating controller. The D flip-flop generates an output signal according to a data signal and a gated clock signal. The gating controller receives an original clock signal. The gating controller further compares the output signal with the data signal. If the output signal is the same as the data signal, the gating controller will maintain the gated clock signal at a constant logic level. If the output signal is different from the data signal, the gating controller will use the original clock signal as the gated clock signal.

A semiconductor integrated circuit connected between a first node and a second node includes first to fourth transistors. When a signal at the second node changes, the fourth transistor is turned on, and a potential obtained by shifting a third potential by the threshold of the fourth transistor is applied to the gate of the second transistor.

A semiconductor integrated circuit connected between a first node and a second node includes first to fourth transistors. When a signal at the second node changes, the fourth transistor is turned on, and a potential obtained by shifting a third potential by the threshold of the fourth transistor is applied to the gate of the second transistor.

A semiconductor integrated circuit connected between a first node and a second node includes first to fourth transistors. When a signal at the second node changes, the fourth transistor is turned on, and a potential obtained by shifting a third potential by the threshold of the fourth transistor is applied to the gate of the second transistor.

A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed.

A flip-flop circuit includes a D flip-flop and a gating controller. The D flip-flop generates an output signal according to a data signal and a gated clock signal. The gating controller receives an original clock signal. The gating controller further compares the output signal with the data signal. If the output signal is the same as the data signal, the gating controller will maintain the gated clock signal at a constant logic level. If the output signal is different from the data signal, the gating controller will use the original clock signal as the gated clock signal.

A 3D multi-bit flip-flop may include a two tier structure. The two tier structure may include a first tier containing a common clock circuit for the multi-bit flip-flop as well as the clock driven portions of the individual flip-flops and a second tier containing a common scan circuit for the multi-bit flip-flop as well as the non-clock driven portions of the individual flip-flops. Alternatively, the first tier may include the common clock circuit as well as a portion of the individual flip-flops and the second tier may include the common scan circuit as well as the other portion of the individual flip-flops.

The present disclosure relates to a D flip-flop having a multiplexer function, including: a first transmission gate whose data input end is configured to receive a first data signal and whose clock input end is configured to receive a first clock signal; a second transmission gate whose data input end is configured to receive a second data signal and whose clock input end is configured to receive a second clock signal; an inverted latch unit whose data input end is connected to an output end of the first transmission gate and an output end of the second transmission gate and whose clock input end is configured to receive a third clock signal; and an inverter whose input end is connected to an output end of the inverted latch unit and whose output end provides an output of the D flip-flop.