Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. A receiver may use a modulation scheme to communicate information with a host device. The receiver may include a first circuit, a second circuit, a third circuit, and a fourth circuit. Each of the first circuit, the second circuit, the third circuit, and the fourth circuit may determine, for a respective clock phase, a voltage level of a signal modulated using the modulation scheme. The receiver may include a first feedback circuit, a second feedback circuit, a third feedback circuit, and a fourth feedback circuit. The first feedback circuit that may use information received from the first circuit at the first clock phase and modify the signal input into the second circuit for the second clock phase.

The present disclosure includes storage circuits, such latches. In one embodiment, a circuit includes a plurality of latches, each latch including a first N-type transistor formed in a first P-type material, a first P-type transistor formed in a first N-type material, a second N-type transistor formed in a second P-type material, and a second P-type transistor formed in a second N-type material. The first and second N-type transistors are formed in different P-wells and the first and second P-type transistors are formed in different N-wells. In other storage circuits, charge extraction transistors are coupled to data storage nodes and are biased in a nonconductive state. These techniques make the data storage circuits more resilient, for example, to an ionizing particle striking the circuit and generating charge carriers that would otherwise change the state of the storage node.

A triple modular redundancy (TMR) flip-flop includes a set of master-gate-latch circuits including a first set of inputs to receive a first digital signal, and a second set of inputs to receive a clock; and a voting logic circuit including a set of inputs coupled to a set of outputs of the set of master-gate-latch circuits, and an output to generate a second digital signal based on the first digital signal. Another TMR flip-flop includes a set of master-gate-latch circuits to receive a set of digital signals in response to a first edge of a clock, respectively; and latch the set of digital signals in response to a second edge of the clock, respectively; and a voting logic circuit to receive the latched set of digital signals; and generate a second digital signal based on a majority of logic levels of the latched first set of digital signals, respectively.

A triple modular redundancy (TMR) flip-flop includes a set of master-gate-latch circuits including a first set of inputs to receive a first digital signal, and a second set of inputs to receive a clock; and a voting logic circuit including a set of inputs coupled to a set of outputs of the set of master-gate-latch circuits, and an output to generate a second digital signal based on the first digital signal. Another TMR flip-flop includes a set of master-gate-latch circuits to receive a set of digital signals in response to a first edge of a clock, respectively; and latch the set of digital signals in response to a second edge of the clock, respectively; and a voting logic circuit to receive the latched set of digital signals; and generate a second digital signal based on a majority of logic levels of the latched first set of digital signals, respectively.

Disclosed is a level shifter. The level shifter includes a level shifting circuit, a first adjusting circuit, and a second adjusting circuit. The level shifting circuit determines whether to output a first current from a supply voltage line to an output node based on a voltage level of a first node and determines whether to output a second current from the supply voltage line to a third node based on a voltage level of a second node. The first adjusting circuit blocks an output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjusting circuit outputs a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received.

A flip-flop circuit includes a first latch, a second latch and a trigger circuit. The first latch is configured to set a first output signal based on at least a first input signal and a clock signal. The second latch is configured to set a second output signal based on a second input signal and the clock signal. The trigger circuit is coupled with the first latch and the second latch. The trigger circuit is configured to generate the second input signal based on at least the second output signal. The trigger circuit is configured to cause the second input signal to have a first voltage swing or a second voltage swing based on the first output signal and the second output signal. The first voltage swing is different from the second voltage swing.

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

Systems, apparatuses, and methods for implementing low-power flip-flops with balanced clock-to-Q delay are described. A flip-flop includes a primary latch, an upper secondary latch, and a lower secondary latch. The primary latch transmits a data value from an input port to a first node when transparent. The upper secondary latch pulls up a second node when transparent and when the first node is equal to a first value. The second node is a prebuffered data output of the flip-flop. The lower secondary latch pulls down the second node when transparent and when the first node is equal to a second value different from the first value. To ensure the flip-flop has a balanced clock-to-Q delay, a first set of clock signals coupled to transistor gates of the primary latch are delayed with respect to a second set of clock signals coupled to transistor gates of the upper secondary latch.

Disclosed is a level shifter. The level shifter includes a level shifting circuit, a first adjusting circuit, and a second adjusting circuit. The level shifting circuit determines whether to output a first current from a supply voltage line to an output node based on a voltage level of a first node and determines whether to output a second current from the supply voltage line to a third node based on a voltage level of a second node. The first adjusting circuit blocks an output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjusting circuit outputs a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received.

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.