A differential signal input buffer is disclosed. The differential signal input buffer may receive a differential signal that includes a first signal and a second signal and may be divided into a first section and a second section and. The first section may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section may buffer and/or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section may buffer and/or amplify the second signal based on a second level-shifted first signal.

The present application is directed to a level shifting circuit. In one form, a level shifting circuit includes a first inverter, a level shifting unit, and a fast driving unit. The first inverter is configured to invert an input signal received at an input node and to output an inverted input signal to a second input node. The level shifting unit is configured to perform amplitude up-shifting processing on a received input signal. The fast driving unit is configured to pull up an output signal of an output node of the level shifting unit by increasing a discharge current of the level shifting unit when receiving the input signal.

Circuits integrating OR logic and level shifting functionality and methods of operating the same are configured to accommodate different applications. One such circuit comprises first and second transistors coupled in parallel defining first and second nodes, the first transistor being responsive to a first input signal and the second transistor being responsive to a second input signal; a first resistor coupled between a power supply terminal of the circuit and the first node; and a second resistor coupled between the second node and a ground terminal of the circuit. The circuit generates an output signal having a voltage level that is lower than a voltage level of each of the first and second input signals.

According to one embodiment, a semiconductor device includes an I/O circuit. configured to be supplied with a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage, and to receive an input signal based on the first voltage. The I/O circuit includes an enabler circuit configured to be supplied with the second voltage, and to generate a first signal based on the second voltage, and a first level shifter circuit coupled to the enabler circuit, and configured to, based on the first signal, level-shift a signal based on the second voltage to a signal based on the third voltage.

Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.

A level shifter for outputting an output voltage having a voltage level range different from a voltage level range of a received input voltage is disclosed. The level shifter includes: a current mirror configured to copy a reference current flowing through a first mirror transistor to a second mirror transistor; a current mirror control circuit electrically connected to the current mirror by a sink node and including a plurality of control transistors configured to control the current mirror; and an output circuit configured to output an output voltage based on a voltage level of the sink node, wherein a first control transistor of the plurality of control transistors receives the output voltage fed back to a gate terminal of the first control transistor, and a second control transistor of the plurality of control transistors receives an inverted output voltage fed back to a gate terminal of the second control transistor.

A power switch circuit comprises a first level shifter configured to turn on a first switching element configured to receive a supply voltage from an external voltage supply pad in response to a program operation of a one-time programmable (OTP) memory cell array, a second level shifter configured to turn on a second switching element and provide the supply voltage to the OTP memory cell array in response to the program operation, a third level shifter configured to turn on a third switching element and provide an internally generated power voltage to the OTP memory cell array in response to a read operation of the OTP memory cell array, and an Electro-Static Discharge (ESD) protection circuit configured to turn off the first switching element in response to a flow of ESD voltage from the voltage supply pad.

An image sensor includes a shifting circuit shifting a first voltage that is applied to a first node, to a second voltage, and shifting the second voltage that is applied to a second node, to the first voltage, and a sub-circuit providing the first voltage to the shifting circuit. The image sensor further includes a source circuit enabling the sub-circuit to provide the first voltage to the shifting circuit, and an enable transistor that is gated by an enable signal, and enables the shifting circuit by providing the second voltage to the shifting circuit, based on the enable signal.

A display system includes a pixel array, an antenna, a reader circuit, and a gate driver circuit. The antenna is configured to transmit a radio frequency (RF) signal in response to a wireless communication. The reader circuit is coupled to the antenna and is configured to receive the RF signal. The gate driver circuit is coupled to the reader circuit and the pixel array. The reader circuit is further configured to generate a clock signal according to the RF signal and transmit the clock signal to the gate drive circuit. The gate driver circuit is configured to generate scanning signals according to the clock signal and transmit the scanning signals to the pixel array.

Described is a high speed, low power level shifter circuit which includes a cross-coupled level shifter coupled to a sensing circuit. The sensing circuit turns off a cross-coupled node of a pair of cross-coupled nodes based on detecting that an input voltage has crossed a threshold voltage for a cross-coupled input transistor of a pair of cross-coupled input transistors, i.e. due to switching from a current logic level to an incoming logic level. Once the sensing circuit detects a threshold voltage crossing, a pull-up circuit pulls high a cross-coupled node and cross-coupled source transistor tied to the cross-coupled node. This turns off the cross-coupled source transistor and turns on another cross-coupled source transistor. Two parallel paths are now established to pull the cross-coupled node high, enabling a high-speed transition. The turning off of the cross-coupled source transistor also pulls the output to the incoming logic level.