This disclosure relates to systems and/or methods for subtracting in the current domain an output current primary signal from a primary sensor from an output current reference signal from a reference sensor to produce a frequency output signal indicative of the difference between the output current primary signal and the output current reference signal.

This disclosure relates to systems and/or methods for subtracting in the current domain an output current primary signal from a primary sensor from an output current reference signal from a reference sensor to produce a frequency output signal indicative of the difference between the output current primary signal and the output current reference signal.

A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.

Relax oscillation circuits have at least one comparison circuit that is structured with a flipped gate transistor and a normal MOS transistor wherein the two transistors having different threshold voltages. The relaxation oscillators are configured for charging and discharging capacitances between the threshold voltages of the flipped gate transistor and the normal MOS transistor by toggling the state of a latching circuit to control the charging and discharging of the capacitances.

An RC oscillator is provided for improving stability of oscillation frequency. The circuit includes an input module, an oscillating module, an inverting module, first and second compensating modules and an output module, wherein the input module provides two-path charging currents and bias current for the oscillating module; the oscillating module outputs a first high level or a first low level to the inverting module under the control of the two-path charging currents and bias current, and improves frequency tuning accuracy of the oscillator; the inverting module inverts the first high level to a second low level or inverts the first low level to a second high level, and outputs the second low level or the second high level to the output module; the output module outputs the second high level and the second low level; and the first and second compensating modules improve stability of the oscillation frequency.

An RC oscillator is provided for improving stability of oscillation frequency. The circuit includes an input module, an oscillating module, an inverting module, first and second compensating modules and an output module, wherein the input module provides two-path charging currents and bias current for the oscillating module; the oscillating module outputs a first high level or a first low level to the inverting module under the control of the two-path charging currents and bias current, and improves frequency tuning accuracy of the oscillator; the inverting module inverts the first high level to a second low level or inverts the first low level to a second high level, and outputs the second low level or the second high level to the output module; the output module outputs the second high level and the second low level; and the first and second compensating modules improve stability of the oscillation frequency.

An oscillator circuit includes a signal generating circuit and a reference voltage generating circuit. The signal generating circuit is configured to receive a reference voltage and generate an output signal according to a comparison result of the reference voltage and a feedback voltage. The feedback voltage is pre-charged to a level of a system high voltage. The reference voltage generating circuit is coupled to the signal generating circuit and configured to generate the reference voltage.

An oscillator circuit includes a signal generating circuit and a reference voltage generating circuit. The signal generating circuit is configured to receive a reference voltage and generate an output signal according to a comparison result of the reference voltage and a feedback voltage. The feedback voltage is pre-charged to a level of a system high voltage. The reference voltage generating circuit is coupled to the signal generating circuit and configured to generate the reference voltage.

An RC oscillator generates a periodic trigger signal, and a clock generator generates clock edges in response. A stuck-at-fault detection circuit detects a stuck-at-logic state of the periodic trigger signal and causes the RC oscillator to reset and causes a change in logic state of the periodic trigger signal. The RC oscillator includes first and second comparison circuits, a logic circuit receiving output from the first and second comparison circuits and generating the periodic trigger signal, and a clock generation circuit generating a clock signal therefrom. The stuck-at-fault detection circuit includes a capacitive node, charge circuitry charging the capacitive node based upon the periodic trigger signal, discharge circuitry discharging the capacitive node based upon the periodic trigger signal, and triggering circuitry asserting a reset signal to cause the RC oscillator to reset when the charge on the capacitive node indicates a stuck-at-logic state of the periodic trigger signal.

An RC oscillator generates a periodic trigger signal, and a clock generator generates clock edges in response. A stuck-at-fault detection circuit detects a stuck-at-logic state of the periodic trigger signal and causes the RC oscillator to reset and causes a change in logic state of the periodic trigger signal. The RC oscillator includes first and second comparison circuits, a logic circuit receiving output from the first and second comparison circuits and generating the periodic trigger signal, and a clock generation circuit generating a clock signal therefrom. The stuck-at-fault detection circuit includes a capacitive node, charge circuitry charging the capacitive node based upon the periodic trigger signal, discharge circuitry discharging the capacitive node based upon the periodic trigger signal, and triggering circuitry asserting a reset signal to cause the RC oscillator to reset when the charge on the capacitive node indicates a stuck-at-logic state of the periodic trigger signal.