Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.

A charge pump device includes first to third current source circuits, a first switch, and a second switch. The first current source circuit is implemented with a first type transistor, and provides a first current to an output node. The first switch is selectively turned on according to a first control signal. When the first switch is turned on, the second current source circuit drains a second current from the output node. The second switch is selectively turned on according to a second control signal. Each of the first switch and the second switch is implemented with a second type transistor, and a withstand voltage of the first type transistor is higher than a withstand voltage of the second type transistor. When the second switch is turned on, the third current source circuit drains a third current from the output node.

A start-up phase of a phase lock loop (PLL) circuit includes supplying, by a phase comparator, of control pulses during which an output signal frequency of an oscillator increases. The increase includes an application of a pre-charge current at the oscillator input. A determination is made of a time variation of the output signal frequency. At least one adjustment is made of the intensity of the pre-charge current depending on the at least one determined time variation so as to approach a reference time variation.

A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

A phase-locked loop circuit includes a phase frequency detector (PHD) circuit, a digital code generator circuit, a frequency divider and an oscillator circuit. The PFD circuit is configured to detect a difference in phase and frequency between a reference clock and a feedback clock to generate a first control signal and a second control signal. The digital code generator circuit is configured to process the second control signal to generate a digital code. The frequency divider is configured to receive an output clock to generate the feedback clock. The oscillator circuit is configured to generate the output clock according to the first control signal and the digital code. A frequency of the output clock is determined according to a first control parameter and a second control parameter of different types. The first and second control parameters are adjusted in response to the first control signal and the digital code respectively.

Apparatus and methods for timing offset compensation of frequency synthesizers are provided herein. In certain embodiments, an electronic system includes a frequency synthesizer, such as a fractional-N phase-locked loop (PLL), which generates an output clock signal based on timing of a reference clock signal. Additionally, the electronic system includes an integer PLL configured to compensate for a timing offset, such as a phase offset and/or frequency offset, of the frequency synthesizer based on timing of the output clock signal.

There is configured a charge pump circuit for outputting a phase difference current to a first node, the charge pump circuit including a first current source coupled between a high potential power supply node and the first node, a second current source coupled between a low potential power supply node and the first node, a first switch coupled between the first current source and the first node, a second switch coupled between the second current source and the first node, a third switch coupled between the first current source and a second node, a fourth switch coupled between the second current source and the second node, a third current source for supplying a negative offset current to the first node, and a push-type differential amplifier circuit an input side of which is coupled to the first node, and an output side of which is coupled to the second node.

A charge pump includes: a switch circuit that switches a current source conducted to an output node based on a signal from a phase frequency detector included in a PLL circuit; a first current source that is the current source provided between a high potential node and the switch circuit, and supplies a current to the output node by a first conduction-type depletion mode MOS transistor forming a self-bias circuit; and a second current source that is the current source provided between a low potential node and the switch circuit, and draws the current from the output node by the first conduction-type depletion mode MOS transistor forming the self-bias circuit.

A delay line includes first to n-th delay cells and a dummy delay cell, ‘n’ being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to n-th output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n−1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding delay cell, and a delay amount of the n-th delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.

An apparatus is disclosed that implements a phase-locked loop (PLL) that uses multiple error determiners as part of a feedback loop. In an example aspect, an apparatus for generating a frequency includes a PLL. The PLL includes a loop filter, a voltage-controlled oscillator (VCO), a frequency divider, and multiple error determiners. The loop filter includes a filter input node and a filter output node. The VCO includes a VCO input node and a VCO output node. The VCO input node is coupled to the filter output node. The frequency divider includes a divider input node and multiple divider output nodes. The divider input node is coupled to the VCO output node. The multiple error determiners are coupled between the multiple divider output nodes and the filter input node.