A phase locked loop of the present disclosure includes a phase comparator circuit, a loop filter, an oscillator circuit, an AD converter circuit, and a current generator circuit. The phase comparator circuit compares a phase of a first signal and a phase of a second signal based on a clock signal. The loop filter includes a resistor element and a capacitor element, and generates a control voltage on the basis of a phase comparison result of the phase comparator circuit. The resistor element has one end coupled to a first node and another end coupled to a second node. The capacitor element has one end coupled to the second node. The oscillator circuit generates the clock signal on the basis of the control voltage. The AD converter circuit converts a voltage difference between the two ends of the resistor element into a digital code. The current generator circuit generates a first current on the basis of the digital code and supplies the first current to the second node.

Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.

A delay line includes first to n-th delay cells and a dummy delay cell, n being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to nth output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding to delay cell, and a delay amount of the nth delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.

A lock detection circuit is configured to include an integrating circuit that integrates a phase difference between a frequency-divided signal of a VCO and a reference signal during a constant period within a transient response period for an output signal from the VCO, and integrates a phase difference between the frequency-divided signal and the reference signal during a constant period within a convergence period for the output signal from the VCO; and a degree-of-convergence calculating circuit that calculates a degree at which the output signal from the VCO has converged, from a result of the integration of the phase difference obtained by the integrating circuit during the constant period within the transient response period and a result of the integration of the phase difference obtained by the integrating circuit during the constant period within the convergence period.

The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.

A clock generation circuit is disclosed. The clock generation circuit includes a logic gate configured to, in response to a control input receiving a first control signal, generate an output clock based on a first input clock received by a first identified clock input. The logic gate is further configured to, in response to the control input receiving the second control signal, generate the output clock based on a fixed logic level. The logic gate is further configured to, in response to the control input receiving the second control signal, generate the output clock based on the second input clock.

A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

In described examples, a phase locked loop (PLL) includes a compensation circuit, a transconductance circuit, and an oscillator. The compensation circuit includes a capacitor circuit and a resistive element having a resistance responsive to a center frequency of the PLL's bandwidth. The transconductance circuit includes a current source and an error amplifier. The current source generates a current responsive to the center frequency. The error amplifier has a transconductance responsive to the center frequency, and receives a signal responsive to the resistance and a difference between an input clock signal and a feedback signal. The oscillator input is coupled to the error amplifier output. The oscillator provides a signal at its output for generating the feedback signal.

An apparatus comprises a first circuit and a second circuit. The first circuit may be configured to generate an output signal having a first frequency in response to a voltage level of a first input signal and a value of a second input signal. The second circuit may be configured to determine the value of the second input signal based on a reference frequency signal, the first frequency of the output signal, a reference voltage, and a value representing a target frequency for the output signal.

A clock generator including a phase frequency detector configured to compare a phase and a frequency of a reference clock signal with a phase and a frequency of a first output clock signal and generate a detection signal based on a difference in the phases and frequencies of the clock signals; a loop filter configured to generate a first control voltage signal based on the detection signal; a first voltage controlled oscillator configured to generate and output a first output clock signal based on the first control voltage signal, a modulation filter configured to generate a modulation voltage signal based on the reference clock signal and generate a second control voltage signal by combining the modulation voltage signal and the first control voltage signal, and a second voltage controlled oscillator configured to generate and output a second output clock signal based on the second control voltage signal is provided.