A driver circuit comprises a first transistor coupled to a second transistor, and a third transistor coupled to the first and second transistor and to a first current mirror. An output of the first current mirror is provided to a control input of the second transistor. A second current mirror is coupled to the output of the first current mirror. A first current source, a second current source, and a fourth transistor are coupled to the second current mirror. The second current source is further coupled to a fifth transistor. A sixth transistor is coupled to the fifth transistor and to a third current mirror. In some implementations, the driver circuit is coupled to a low side transistor in an H bridge driver and the second transistor is matched to the low side transistor.

The present invention provides a clock generating circuit, wherein the clock generating circuit includes a phase detector, an integral path, a proportional path, a bias path and an oscillator. In the operations of the clock generating circuit, the phase detector generates a detection result according to a reference signal and a feedback signal, a first charge pump within the integral path generates a first control signal according to the detection result, a second charge pump within proportional path generates a second control signal according to the detection result, a low-pass filter within the bias path filters the first control signal to generate a third control signal, and the oscillator generates a clock signal according to the first control signal, the second control signal and the third control signal.

The disclosure relates to voltage-controlled-oscillator circuit comprising: a charge-pump configured to generate a tuning-voltage, the tuning-voltage having a minimum-operating-voltage; an offset-voltage-source configured to generate an offset-voltage in accordance with the minimum-operating-voltage; and a voltage-controlled-oscillator, VCO, configured to provide an oscillator frequency in accordance with the tuning-voltage and the offset-voltage.

A first transistor and a second transistor have control terminals coupled to each other. A current mirror circuit supplies a current having the same amount as that of a current I.sub.ref flowing through a first path including the second transistor to a second path including the first transistor and supplies a current having a predetermined number of times m of a current amount of the current I.sub.ref of the first path to a third path separate from the second path. The third transistor and a fourth transistor are provided on the third path. The third transistor has a source coupled to one end of the first transistor, and the fourth transistor has a gate coupled to a gate of the third transistor. A resistor is provided between a source of the fourth transistor and one end of the second transistor.

A unity gain buffer is shared by a charge pump and an active loop filter in a phase-locked loop. The charge pump uses the unity gain buffer to reduce current mismatch in the charge pump and the active loop filter uses the unity gain buffer in a circuit that increases the effective capacitance of the active loop filter.

Disclosed is a device including a sinking circuit to sink current from an output node and a driver circuit coupled to the sinking circuit. The driver circuit includes complementary differential pairs to receive a voltage at the output node and generate a control signal according to the received voltage. The sinking circuit is configured to change the current from the output node according to the control signal.

A delay-locked loop circuit includes first and second duty cycle correctors, and first and second duty cycle detectors. The first duty cycle corrector adjusts duties of some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code. The second duty cycle corrector adjusts delays of some of second through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code. The first duty cycle detector detects a duty of first propagation clock signal to generate a first sub-correction code of the first correction code, and duties of first and second recovered clock signals to generate the second correction code. The second duty cycle detector detects a duty of second propagation clock signal to generate a second sub-correction code of the first correction code.

Described is a low power and low jitter phase locked loop (PLL) or delay locked loop (DLL) with digital leakage compensation. The compensation is provided by an apparatus which comprises: a circuitry to generate a pulse with a digitally controlled pulse width, wherein the pulse width is proportional to a static phase error of a PLL or a DLL; and a charge pump coupled to the circuitry, wherein the charge pump is to receive the pulse and to source or sink current to or from a node according to the pulse width.

Described is a low power and low jitter phase locked loop (PLL) or delay locked loop (DLL) with digital leakage compensation. The compensation is provided by an apparatus which comprises: a circuitry to generate a pulse with a digitally controlled pulse width, wherein the pulse width is proportional to a static phase error of a PLL or a DLL; and a charge pump coupled to the circuitry, wherein the charge pump is to receive the pulse and to source or sink current to or from a node according to the pulse width.

A temperature sensor using a poly-phase filter may include: a poly-phase filter suitable for receiving a divided clock, and having passive elements coupled to have one or more negative poles and one or more positive zeros; a comparator suitable for generating a reference clock by comparing potentials of first and second filter voltages outputted from the poly-phase filter; a phase frequency detector suitable for outputting an up or down signal by comparing the phase of the reference clock to the phase of a comparison clock; a current supply unit suitable for supplying and integrating a charge current under control of the up or the down signal; an oscillator suitable for outputting an oscillation signal; a divider suitable for generating the divided clock and the comparison clock; and a buffer suitable for inverting and non-inverting the divided clock and outputting the inverted and non-inverted divided clocks.