A phase-locked loop circuit includes a voltage controlled oscillator (VCO) that generates a VCO clock in response to a voltage control signal, a divider that divides the VCO clock to output a division clock, a phase-frequency error detector that receives a reference clock and outputs a first error compensation signal, a sampler that receives the reference clock and oversamples the reference clock at a rising edge or a falling edge to output a sampling clock, a window phase error detector that receives the reference clock and outputs a second error compensation signal, a residue phase error detector that outputs a third error compensation signal, an adder that accumulates the first error compensation signal, the second error compensation signal, and the third error compensation signal to output a final error compensation signal, and a loop filter that converts and output the final error compensation signal into the voltage control signal.

An integrated circuit includes an on-chip PLL response measurement capability. The PLL response is determined in terms of PLL bandwidth and PLL peaking. A digital phase offset is inserted to a digital representation of a first clock signal to create a phase step. A phase and frequency detector of a phase-locked loop (PLL) supplies a phase error signal indicative of a difference between the first clock signal and a second clock signal. The elapsed time between the phase step insertion and the first zero crossing of the phase error as the PLL tries to deal with the is used to determine PLL bandwidth. The maximum phase error overshoot resulting from insertion of the digital phase offset is determined for use in determining PLL peaking.

An integrated circuit includes an on-chip PLL response measurement capability. The PLL response is determined in terms of PLL bandwidth and PLL peaking. A digital phase offset is inserted to a digital representation of a first clock signal to create a phase step. A phase and frequency detector of a phase-locked loop (PLL) supplies a phase error signal indicative of a difference between the first clock signal and a second clock signal. The elapsed time between the phase step insertion and the first zero crossing of the phase error as the PLL tries to deal with the is used to determine PLL bandwidth. The maximum phase error overshoot resulting from insertion of the digital phase offset is determined for use in determining PLL peaking.

An oscillator is provided. The oscillator is configured for generating an output signal which is phase locked to an input signal. The oscillator comprises a controlled oscillator configured for generating the output signal based on an oscillator input signal. Moreover, the oscillator comprises a frequency divider configured for dividing the frequency of the output signal, resulting in a frequency divided feedback signal. Also, the oscillator comprises a phase detector, which is configured for generating an error signal based upon the frequency divided feedback signal and the input signal. Also, the oscillator comprises an error signal pulse train modulator configured for generating the oscillator input signal by performing a pulse train modulation of the error signal) or a signal derived from the error signal based on the input signal.

A clock data recovery circuit is disclosed. The clock data recovery circuit includes a bit stream data rate divider and a digital phase-locked loop including a linear phase detector. The bit stream data rate divider is configured to divide a frequency of a serial data stream by a designated division factor to generate a divided serial data stream. The linear phase detector is configured to compare phases of the divided serial data stream and a feedback signal within the digital phase-locked loop and output an UP signal associated with phase lagging and a DOWN signal associated with phase leading of the feedback signal versus the divided serial data stream. The digital phase-locked loop is configured to output a clock signal having a phase based on a digital difference between a digitized-UP signal derived from the UP signal and a digitized-DOWN signal derived from the DOWN signal.

An oscillator is provided. The oscillator is configured for generating an output signal which is phase locked to an input signal. The oscillator comprises a controlled oscillator configured for generating the output signal based on an oscillator input signal. Moreover, the oscillator comprises a frequency divider configured for dividing the frequency of the output signal, resulting in a frequency divided feedback signal. Also, the oscillator comprises a phase detector, which is configured for generating an error signal based upon the frequency divided feedback signal and the input signal. Also, the oscillator comprises an error signal pulse train modulator configured for generating the oscillator input signal by performing a pulse train modulation of the error signal) or a signal derived from the error signal based on the input signal.

A phase-locked loop circuit includes a voltage controlled oscillator (VCO) that generates a VCO clock in response to a voltage control signal, a divider that divides the VCO clock to output a division clock, a phase-frequency error detector that receives a reference clock and outputs a first error compensation signal, a sampler that receives the reference clock and oversamples the reference clock at a rising edge or a falling edge to output a sampling clock, a window phase error detector that receives the reference clock and outputs a second error compensation signal, a residue phase error detector that outputs a third error compensation signal, an adder that accumulates the first error compensation signal, the second error compensation signal, and the third error compensation signal to output a final error compensation signal, and a loop filter that converts and output the final error compensation signal into the voltage control signal.

A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.

A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.